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path: root/riscv/processor.h
AgeCommit message (Expand)AuthorFilesLines
2011-02-04[sim,pk] added interrupt-pending field to cause regAndrew Waterman1-1/+0
2011-01-18[opcodes, sim, xcc] made *w insns illegal in RV32Andrew Waterman1-4/+4
2010-10-26[pk,sim,xcc] get rid of at register, introduce tp registerYunsup Lee1-1/+0
2010-10-05[xcc,sim] eliminated vectored trapsAndrew Waterman1-1/+2
2010-09-09Merge branch 'master' of /project/eecs/parlab/git/projects/riscvAndrew Waterman1-0/+2
2010-09-09[pk, sim] added interrupt support to sim; added timer interruptAndrew Waterman1-0/+3
2010-09-08[sim] add while to interactive_untilYunsup Lee1-0/+2
2010-09-07[sim] yet another fix stdint.h __STDC_LIMIT_MACROS problemYunsup Lee1-1/+1
2010-09-06[sim, xcc] added PCRs to replace k0 and k1Andrew Waterman1-0/+2
2010-09-06[sim, xcc] bthread threading model exposed; insn encoding cleaned upAndrew Waterman1-0/+7
2010-08-24[sim] privileged mode support for 32-bit operationAndrew Waterman1-1/+1
2010-08-09[xcc,sim] implement FP using softfloatAndrew Waterman1-0/+2
2010-08-04[xcc,pk,sim] Added first part of FP supportAndrew Waterman1-0/+1
2010-07-21[pk,sim] first cut of appserver communication linkAndrew Waterman1-1/+6
2010-07-18Reorganized directory structureAndrew Waterman1-0/+40