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AgeCommit message (Expand)AuthorFilesLines
2019-07-22Writing non-existent CSRs, access FPRs with mstatus.FS=0 (#311)Tim Newsome1-1/+6
2019-05-13Revert "Add FLH and FSH instructions expanding IEEE fp16 in memory to fp32 in...Chih-Min Chao1-19/+0
2019-01-21Add FLH and FSH instructions expanding IEEE fp16 in memory to fp32 in registersBruce Hoult1-0/+19
2017-02-15Implement resume (untested).Tim Newsome1-0/+3
2017-02-10Entering debug mode now jumps to "dynamic rom"Tim Newsome1-0/+241
2013-11-25Update to new privileged ISAAndrew Waterman1-158/+0
2013-11-21fix slli/slliw encoding bugYunsup Lee1-2/+2
2013-09-21Update ISA encoding and AUIPC semanticsAndrew Waterman1-156/+154
2013-09-15ISA changesAndrew Waterman1-2/+2
2013-09-11Add AMOXORAndrew Waterman1-16/+18
2013-09-11Implement zany immediatesAndrew Waterman1-6/+6
2013-09-10Add rd field to JAL; drop JAndrew Waterman1-26/+25
2013-08-08Rename MTFSR/MFFSR to FSSR/FRSRAndrew Waterman1-2/+2
2013-08-08Swap J and JALR encodingAndrew Waterman1-2/+2
2013-07-26New supervisor modeAndrew Waterman1-5/+5
2013-07-26Rename MFTX/MXTF to FMVAndrew Waterman1-4/+4
2013-07-26Rip out Hwacha for nowAndrew Waterman1-89/+0
2013-07-26Rip out RVC for nowAndrew Waterman1-34/+0
2013-07-25Remove JALR static hintsAndrew Waterman1-13/+10
2013-04-17add AUIPC insn; remove RDNPC insnAndrew Waterman1-2/+2
2013-03-29add load-reserved/store-conditional instructionsAndrew Waterman1-2/+6
2013-03-27opcodes.h must only contain DECLARE_INSN() linesAndrew Waterman1-2/+0
2013-03-25add BSD licenseAndrew Waterman1-0/+2
2012-03-24new supervisor modeAndrew Waterman1-17/+16
2012-03-18update vector fencesAndrew Waterman1-8/+6
2012-03-18clean up vector exception instructionsYunsup Lee1-8/+10
2012-03-13add more instructions for vector exception handlingYunsup Lee1-4/+7
2012-03-13add vvcfg,vtcfgYunsup Lee1-1/+3
2012-03-13opcodes cleanupYunsup Lee1-8/+7
2012-03-10slight change to vector supervisor instructionsYunsup Lee1-4/+4
2012-03-03new instructions to handle vector exceptionsYunsup Lee1-0/+6
2011-11-11Changed MFTX to use rs1 for its sourceAndrew Waterman1-2/+2
2011-06-19temporary undoing of renamingAndrew Waterman1-0/+272
2011-06-12[sim] renamed to riscv-isa-runAndrew Waterman1-272/+0
2011-06-10[sim, opcodes] made sim more decoupled from opcodesAndrew Waterman1-0/+272
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