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AgeCommit message (Expand)AuthorFilesLines
2011-06-11[xcc] instructions now set PC explicitlyAndrew Waterman14-18/+18
2011-06-10[sim, opcodes] made sim more decoupled from opcodesAndrew Waterman2-2/+2
2011-06-05[sim] fix writeback after ipi clearingAndrew Waterman1-0/+1
2011-06-04[sim] add ability to clear IPIsAndrew Waterman1-0/+3
2011-05-29[sim,opcodes] improved sim build and run performanceAndrew Waterman1-1/+1
2011-05-28[fesvr,xcc,sim] fixed multicore sim for akarosAndrew Waterman2-0/+12
2011-05-23[sim,xcc] add rdcycle/rdtime/rdinstretAndrew Waterman3-3/+3
2011-05-19[sim] more fp<->int fixesAndrew Waterman4-4/+4
2011-05-19[sim] more fp conversion bugs fixedAndrew Waterman2-2/+2
2011-05-18[sim] fixed fcvt rounding bugsAndrew Waterman8-8/+8
2011-05-18[opcodes,pk,sim] add more vector traps (for #banks, illegal instructions)Yunsup Lee2-0/+9
2011-05-16[sim,pk] cleanups & initial virtual memory supportAndrew Waterman3-1/+10
2011-05-16[sim,xcc] change cond. mov inst format, add implementationYunsup Lee4-0/+8
2011-05-15[libs,opcodes,pk,sim,xcc] add mov*,fmov*, shuffle vec instsYunsup Lee75-0/+0
2011-05-13[sim] stubs for perfctr instructionsAndrew Waterman3-0/+3
2011-04-24[xcc,sim,opcodes] added c.addiwAndrew Waterman1-0/+3
2011-04-24[xcc,sim,opcodes] added more RVC instructionsAndrew Waterman20-1/+65
2011-04-23[sim] fixed divw/remw crashing simulatorAndrew Waterman2-6/+2
2011-04-18[xcc,sim] rv64 'w' instruction semantics changedAndrew Waterman2-2/+2
2011-04-18[xcc,sim,opcodes] added rvc conditional branchesAndrew Waterman2-0/+6
2011-04-16[sim] removed undefined behavior for non-canonical inputsAndrew Waterman12-12/+12
2011-04-15[sim] fixed jalr immediate bugAndrew Waterman1-2/+2
2011-04-12[xcc,pk,sim] added privileged cflush instructionAndrew Waterman1-0/+1
2011-04-12[xcc,sim] rvc loads and storesAndrew Waterman8-0/+20
2011-04-11[xcc,sim,opcodes] more rvc instructions and bug fixesAndrew Waterman4-2/+6
2011-04-09[sim] add vector traps to vector instructionsYunsup Lee43-0/+43
2011-04-09[sim] add vt stuffYunsup Lee43-0/+83
2011-04-09[xcc, sim] added rvc insn c.li; misc fixesAndrew Waterman1-0/+2
2011-04-09[xcc,pk,sim,opcodes] added first RVC instructionAndrew Waterman2-1/+2
2011-04-08[sim] fixed multiply-high in rv32Andrew Waterman2-2/+2
2011-04-05[opcodes,pk,sim,xcc] fix vector mem instruction format, add vector seg mem in...Yunsup Lee36-0/+0
2011-04-04[opcodes,pk,sim,xcc] add leftover vector instructions (vf, etc.)Yunsup Lee5-0/+0
2011-04-04[opcodes,pk,sim,xcc] add vector mem instructionsYunsup Lee30-0/+0
2011-04-04[opcodes,pk,sim,xcc] add stop,utidx instructionsYunsup Lee2-0/+0
2011-04-04[opcodes,pk,sim,xcc] add fence instructions for vector unitYunsup Lee4-0/+0
2011-03-30[xcc] fixed bug in amo{maxu,minu}.wAndrew Waterman2-2/+2
2011-03-25[sim,pk,xcc,opcodes] removed fminmag/fmaxmagAndrew Waterman4-24/+0
2011-03-25[xcc,pk,opcodes,sim] updated encoding/insn namesAndrew Waterman12-0/+43
2011-03-17[sim] LWU now illegal in RV32Andrew Waterman1-0/+1
2011-02-15[xcc,opcodes,pk,sim] krste's re-renaming spreeAndrew Waterman39-0/+0
2011-02-15[xcc,sim,opcodes] removed mtflh/mffl/mffhAndrew Waterman3-9/+0
2011-02-04[sim,pk] added interrupt-pending field to cause regAndrew Waterman1-1/+1
2011-02-02[sim,xcc,opcodes] added back mtflh.dAndrew Waterman2-4/+5
2011-02-01[xcc,opcodes,pk,sim] cleanup to FP ISAAndrew Waterman8-29/+10
2011-01-26[sim] changed divide-by-0 semanticsAndrew Waterman2-9/+8
2011-01-25[sim,opcodes] add mulhsu instructionAndrew Waterman1-0/+8
2011-01-25[opcodes,pk,sim,xcc] great renumbering of 2011, part deuxAndrew Waterman2-6/+0
2011-01-20[sim, pk, xcc, opcodes] great instruction renaming of 2011Andrew Waterman83-8/+14
2011-01-18[opcodes, sim, xcc] made *w insns illegal in RV32Andrew Waterman54-76/+113
2011-01-17[opcodes, pk, sim, xcc] removed nor, normalized macros to addiAndrew Waterman1-1/+0
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