| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2011-01-18 | [opcodes, sim, xcc] made *w insns illegal in RV32 | Andrew Waterman | 1 | -1/+1 |
| 2010-11-21 | [xcc, sim, pk, opcodes] new instruction encoding! | Andrew Waterman | 1 | -1/+1 |
| 2010-10-05 | [xcc,sim] eliminated vectored traps | Andrew Waterman | 1 | -1/+4 |
| 2010-09-20 | [xcc, sim] changed instruction format so imm12 subs for rs2 | Andrew Waterman | 1 | -2/+2 |
| 2010-09-09 | Merge branch 'master' of /project/eecs/parlab/git/projects/riscv | Andrew Waterman | 1 | -1/+1 |
| 2010-09-09 | [pk, sim] added interrupt support to sim; added timer interrupt | Andrew Waterman | 1 | -0/+6 |
| 2010-09-08 | [sim] add while to interactive_until | Yunsup Lee | 1 | -1/+1 |
| 2010-09-06 | [sim, xcc] added PCRs to replace k0 and k1 | Andrew Waterman | 1 | -0/+7 |
| 2010-09-06 | [sim, xcc] bthread threading model exposed; insn encoding cleaned up | Andrew Waterman | 1 | -1/+1 |
| 2010-08-24 | [sim] privileged mode support for 32-bit operation | Andrew Waterman | 1 | -8/+11 |
| 2010-08-03 | [pk,sim,xcc] Renamed instructions to RISC-V spec | Andrew Waterman | 1 | -0/+29 |
