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Maybe some day we can bring it back, implementing direct access into
registers and memory so it would be fast. That would be the way to
usefully debug code running in spike, as opposed to the way that mirrors
the actual debug design as it might be implemented in hardware.
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Temporarily turn them on in mstatus if necessary.
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Newer gdbs send larger memory write packets when downloading.
Also improve error reporting when gdb sends packets that don't fit in
the buffer.
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Instead, just give gdb what it asks for.
Also when gdb does a register write, let the user know that it's likely
misconfigured and tell them how to fix it.
This is probably as well as issue #72 can be fixed in spike.
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So far I only have testcases for instruction and data address.
Not implemented is the mechanism that lets the debugger prevent a user
program from using triggers at all. I'll be adding that soonish.
The critical path is unchanged, but my experimenting shows the
simulation is slowed down about 8% by this code. Reducing the size of
trigger_match() (which is never called during my benchmark) fixes that,
but making it not be inlined has no effect. I suspect the slowdown comes
from cache alignment or something similar, and on a different CPU or
after more code changes the speed will come back.
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Users can use this register to inspect and change the privilege level of
the core. It doesn't make any assumptions about the actual underlying
debug mechanism (as opposed to having the user change DCSR directly,
which may not exist in all debug implementations).
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This doesn't change anything since Debug ROM already executes a fence.i,
but it will be more correct if that is no longer necessary.
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in preparation for address translation.
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Also read DCSR, which will be useful to figure out why we halted.
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Also clear dcsr.cause when leaving Debug Mode so future traps go where
they should.
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I think the functionality is unchanged.
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(gdb) target remote localhost:1234
Remote debugging using localhost:1234
0x0000000000010178 in fib (n=0) at waste.c:1
1 unsigned int fib(unsigned int n) {
(gdb)
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This should replace the ROM hack I implemented earlier, but for now both
exist together.
Back to the point where gdb connects, core jumps to ROM->RAM->ROM.
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It's necessary to be able to run multiple spikes at once on the same
box.
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Also set the simulation running again when gdb disconnects.
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The endianness is wrong, but I think it might be that gdb doesn't have
it right. Need to investigate what architecture gdb thinks it's
debugging.
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So far it just listens, and gdb times out because it's not getting any
messages back.
Receive packets and verify their checksum.
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