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path: root/riscv/execute.h
AgeCommit message (Expand)AuthorFilesLines
2011-02-15[xcc,opcodes,pk,sim] krste's re-renaming spreeAndrew Waterman1-93/+93
2011-02-15[xcc,sim,opcodes] removed mtflh/mffl/mffhAndrew Waterman1-15/+0
2011-02-02[sim,xcc,opcodes] added back mtflh.dAndrew Waterman1-1/+6
2011-02-02[opcodes,pk,sim,xcc] synci now bombs whole icacheAndrew Waterman1-9/+9
2011-02-01[xcc,opcodes,pk,sim] cleanup to FP ISAAndrew Waterman1-108/+103
2011-01-25[sim,opcodes] add mulhsu instructionAndrew Waterman1-1/+6
2011-01-25[opcodes,pk,sim,xcc] great renumbering of 2011, part deuxAndrew Waterman1-527/+527
2011-01-20[sim, pk, xcc, opcodes] great instruction renaming of 2011Andrew Waterman1-143/+172
2011-01-18[opcodes, sim, xcc] made *w insns illegal in RV32Andrew Waterman1-10/+0
2011-01-17[opcodes, pk, sim, xcc] removed nor, normalized macros to addiAndrew Waterman1-5/+0
2011-01-03[opcodes,pk,sim,xcc] flip fields to favor little endianYunsup Lee1-139/+143
2010-11-21[opcodes, pk, sim, xcc] Tweaked FP encodingAndrew Waterman1-229/+64
2010-11-21[opcodes] generate latex and verilog correctlyAndrew Waterman1-67/+67
2010-11-21[xcc, sim, pk, opcodes] new instruction encoding!Andrew Waterman1-331/+325
2010-11-21[opcodes, pk, sim, xcc] made jumps shorter and PC-relativeAndrew Waterman1-30/+0
2010-10-25[sim,xcc,pk,opcodes] static rounding modes for FP insnsAndrew Waterman1-46/+228
2010-10-15[pk, sim] added FPU emulation support to proxy kernelAndrew Waterman1-1/+1
2010-10-07[xcc] modified opcodes for better FP decode mappingAndrew Waterman1-27/+19
2010-10-05[opcodes] added code field back to syscall/breakAndrew Waterman1-2/+2
2010-10-02[xcc, sim] mff now uses rs2 for dataAndrew Waterman1-45/+45
2010-09-28[opcodes, sim, xcc] added mffl.d instructionAndrew Waterman1-108/+113
2010-09-20[xcc, sim] changed instruction format so imm12 subs for rs2Andrew Waterman1-30/+30
2010-09-13[xcc, sim] replaced ble/bleu with bge/bgeuAndrew Waterman1-7/+7
2010-09-12[sim] renamed sllv to sll (same for other shifts)Andrew Waterman1-29/+29
2010-09-12[xcc, sim] moved shamt field and renamed shiftsAndrew Waterman1-75/+59
2010-09-12[xcc, sim] branches now are next-PC-based, not PC-basedAndrew Waterman1-6/+6
2010-09-10[sim, xcc] Added mffh.d/mtflh.d; fixed FP ABI for 32-bitAndrew Waterman1-4/+4
2010-09-10[opcodes,xcc,sim] mffh.d,mtfh.d added (broken commit)Yunsup Lee1-147/+148
2010-09-09[opcodes,sim,xcc] move opcodes for 3 source instructionsYunsup Lee1-56/+67
2010-09-09Revert "[xcc, sim] added slei/sleui in lieu of slti/sltiu"Andrew Waterman1-2/+2
2010-09-07[xcc, sim] added slei/sleui in lieu of slti/sltiuAndrew Waterman1-2/+2
2010-09-06[sim, xcc] bthread threading model exposed; insn encoding cleaned upAndrew Waterman1-30/+21
2010-09-06[sim] added atomic memory operationsAndrew Waterman1-18/+128
2010-08-22[xcc,sim] added fused multiply-add and its cousinsAndrew Waterman1-0/+56
2010-08-22[xcc,sim] Eliminated slori instructionAndrew Waterman1-5/+0
2010-08-09[xcc,sim] implement FP using softfloatAndrew Waterman1-226/+58
2010-08-05[sim,xcc] Added first few Hauser FP insns (sign-injection)Andrew Waterman1-44/+56
2010-08-04[xcc] Removed ctc1, cfc1 instructions; added fp move test caseAndrew Waterman1-18/+0
2010-08-04[xcc,pk,sim] Added first part of FP supportAndrew Waterman1-22/+4
2010-08-03[sim,xcc] removed sll32/srl32/sra32 opcodesAndrew Waterman1-18/+3
2010-08-03[pk,sim,xcc] Renamed instructions to RISC-V specAndrew Waterman1-38/+38
2010-07-28[sim,xcc] Changed instruction format to RISC-VAndrew Waterman1-562/+1074
2010-07-18Reorganized directory structureAndrew Waterman1-0/+635