Age | Commit message (Expand) | Author | Files | Lines |
2014-12-04 | Support 2/4/6/8-byte instructions | Andrew Waterman | 1 | -19/+21 |
2014-12-04 | Set badvaddr on instruction page faults | Andrew Waterman | 1 | -1/+1 |
2014-11-30 | Implement timer faithfully | Andrew Waterman | 1 | -2/+0 |
2014-09-27 | Avoid use of __int128_t | Andrew Waterman | 1 | -5/+1 |
2014-07-08 | Disallow access to FCSR when FP is disabled | Andrew Waterman | 1 | -17/+18 |
2014-06-13 | Commit log now prints while interrupts are enabled. | Christopher Celio | 1 | -6/+2 |
2014-06-13 | Only print commit log if instruction commits | Andrew Waterman | 1 | -2/+2 |
2014-01-24 | Handle CSR permissions correctly | Andrew Waterman | 1 | -5/+6 |
2014-01-13 | Improve performance for branchy code | Andrew Waterman | 1 | -3/+6 |
2013-12-17 | Speed things up quite a bit | Andrew Waterman | 1 | -11/+11 |
2013-12-09 | New RDCYCLE encoding | Andrew Waterman | 1 | -2/+3 |
2013-11-25 | Update to new privileged ISA | Andrew Waterman | 1 | -6/+9 |
2013-11-05 | correctly trap when SR_EA is disabled | Yunsup Lee | 1 | -0/+1 |
2013-09-27 | Added commit logging (--enable-commitlog). Also fixed disasm bug. | Christopher Celio | 1 | -0/+27 |
2013-09-27 | Use WRITE_RD/WRITE_FRD macros to write registers | Andrew Waterman | 1 | -22/+4 |
2013-09-21 | Update ISA encoding and AUIPC semantics | Andrew Waterman | 1 | -11/+15 |
2013-09-11 | Implement zany immediates | Andrew Waterman | 1 | -91/+30 |
2013-09-10 | Add rd field to JAL; drop J | Andrew Waterman | 1 | -11/+2 |
2013-08-11 | Instructions are no longer member functions | Andrew Waterman | 1 | -17/+18 |
2013-08-08 | Disentangle some header files | Andrew Waterman | 1 | -0/+1 |
2013-07-26 | Remove more vector stuff | Andrew Waterman | 1 | -60/+3 |
2013-07-26 | Rip out RVC for now | Andrew Waterman | 1 | -27/+11 |
2013-07-26 | Generate instruction decoder dynamically | Andrew Waterman | 1 | -1/+1 |
2013-04-24 | fixes to correctly simulate the vector unit | Yunsup Lee | 1 | -0/+2 |
2013-03-25 | add BSD license | Andrew Waterman | 1 | -0/+2 |
2013-03-25 | truncate effective addresses in rv32 | Andrew Waterman | 1 | -1/+2 |
2013-03-25 | support compilation with gcc 4.7 | Andrew Waterman | 1 | -0/+1 |
2013-01-25 | change htif to link against libfesvr | Andrew Waterman | 1 | -3/+14 |
2012-03-24 | new supervisor mode | Andrew Waterman | 1 | -15/+1 |
2012-03-19 | abstract regfile write port | Andrew Waterman | 1 | -14/+30 |
2012-03-19 | abstract regfile behind object | Andrew Waterman | 1 | -20/+20 |
2012-01-22 | disentangle decode.h from other headers | Andrew Waterman | 1 | -16/+0 |
2012-01-22 | work around gcc 4.4 bug | Andrew Waterman | 1 | -2/+2 |
2011-11-11 | Changed supervisor mode | Andrew Waterman | 1 | -5/+0 |
2011-06-19 | temporary undoing of renaming | Andrew Waterman | 1 | -0/+301 |
2011-06-12 | [sim] renamed to riscv-isa-run | Andrew Waterman | 1 | -301/+0 |
2011-06-12 | [xcc] minor performance tweaks | Andrew Waterman | 1 | -10/+9 |
2011-06-11 | [xcc] instructions now set PC explicitly | Andrew Waterman | 1 | -0/+14 |
2011-05-29 | [sim,opcodes] improved sim build and run performance | Andrew Waterman | 1 | -7/+6 |
2011-05-28 | [fesvr,xcc,sim] fixed multicore sim for akaros | Andrew Waterman | 1 | -0/+1 |
2011-05-18 | [opcodes,pk,sim] add more vector traps (for #banks, illegal instructions) | Yunsup Lee | 1 | -5/+12 |
2011-05-13 | [sim] initial support for virtual memory | Andrew Waterman | 1 | -1/+2 |
2011-04-24 | [xcc,sim,opcodes] added more RVC instructions | Andrew Waterman | 1 | -3/+9 |
2011-04-18 | [xcc,sim,opcodes] added rvc conditional branches | Andrew Waterman | 1 | -4/+7 |
2011-04-16 | [sim] removed undefined behavior for non-canonical inputs | Andrew Waterman | 1 | -1/+3 |
2011-04-12 | [xcc,sim] fixed RM field | Andrew Waterman | 1 | -2/+4 |
2011-04-12 | [xcc,sim] rvc loads and stores | Andrew Waterman | 1 | -1/+7 |
2011-04-11 | [sim] fixed FSR exception field bug | Andrew Waterman | 1 | -1/+1 |
2011-04-11 | [xcc,sim,opcodes] more rvc instructions and bug fixes | Andrew Waterman | 1 | -0/+6 |
2011-04-09 | [sim] add vt stuff | Yunsup Lee | 1 | -0/+45 |