aboutsummaryrefslogtreecommitdiff
path: root/config.h.in
AgeCommit message (Expand)AuthorFilesLines
2017-03-21autoconf: put location of 'dtc' into config.hWesley W. Terpstra1-0/+3
2017-02-18Make HW setting of PTE A/D bits optional (by configure arg)Andrew Waterman1-0/+3
2016-04-02Allow configuration of default ISA with --with-isaAndrew Waterman1-2/+44
2015-04-03Support setting ISA/subsets with --isa flagAndrew Waterman1-9/+0
2015-03-30Implement RVC draftAndrew Waterman1-0/+3
2014-12-29autoreconf 65ba70071d11cc19b3dc85c047c5fea6d4d7bc0dPalmer Dabbelt1-4/+1
2014-11-25Factor out the dummy RoCC acceleratorAndrew Waterman1-0/+3
2014-08-15Added PC histogram option.Christopher Celio1-0/+3
2014-01-26Enable runtime loading of dynamic library with --extlibAndrew Waterman1-1/+1
2014-01-24Require libdl for dynamic linking at runtimeAndrew Waterman1-0/+3
2013-10-17add hwacha exception supportYunsup Lee1-0/+3
2013-10-10commit configure script; new configure option --enable-commitlogYunsup Lee1-0/+3
2013-07-26Remove more vector stuffAndrew Waterman1-6/+0
2013-01-25change htif to link against libfesvrAndrew Waterman1-0/+6
2011-11-11Remove dependence on binutilsYour Name1-3/+0
2011-06-19temporary undoing of renamingAndrew Waterman1-0/+46
2011-06-12[sim] renamed to riscv-isa-runAndrew Waterman1-49/+0
2011-04-15[sim] added icache simulator (disabled by default)Andrew Waterman1-0/+3
2011-04-09[sim] add disable option for vectorYunsup Lee1-0/+3
2011-04-09[sim,pk] reorganized status registerAndrew Waterman1-0/+3
2010-10-15[pk, sim] added FPU emulation support to proxy kernelAndrew Waterman1-0/+6
2010-09-20[xcc, sim] changed instruction format so imm12 subs for rs2Andrew Waterman1-0/+6
2010-07-18Reorganized directory structureAndrew Waterman1-0/+28
generated by cgit v1.1 at 2024-11-17 01:23:14 +0000