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Based on Spec chapter 3.5
"An MRET or SRET instruction is used to return from a trap in M-mode or
S-mode, respectively. When executing an xRET instruction, if xPP holds
the value y, then ELP is set to the value of xPELP if yLPE is 1;
otherwise, it is set to NO_LP_EXPECTED; xPELP is set to NO_LP_EXPECTED."
The change follow the last statement after semicolon
"xPELP is set to NO_LP_EXPECTED"
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Implement mcontrol6.hit
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Avoid using private headers, e.g., debug_defines.h, in triggers.h
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mcontrol6_t::hit
Add mcontrol_common_t::set_hit()
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Update CSR_MCONTROL6_HIT to CSR_MCONTROL6_HIT0
Include CSR_TINFO_VERSION* macros
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Add Zawrs extension
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Zfa: fix: fmaxm.q requires Q instead of D extension
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Remove old P extension
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Support per-device arguments and device factory reuse
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As proposed in #1652, we made the following changes to MMIO device (factory)
plugin API, to mitigate current limitations and facilitate factory reuse.
- removed `sargs` from `device_factory_t`, and introduced a new type alias
`device_factory_sargs_t` to capture `<device_factory_t *, sargs>` pairs,
this is used to instantiate sim_t instances;
- changed the signature of `device_factory_t::generate_fdt` and
`device_factory_t::parse_from_fdt` to take on an extra `sargs` argument,
for instantiating devices with per-device arguments;
- made `device_factory_t` const and potentially resuable across multiple
`sim_t` instances.
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Smstateen: Ignore writes to read-only hstateen*[n] bits when mstateen*[n]=0
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PLIC: Implement threshold masking
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add hlvx pmp protect to fix issue 1557
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Support Zicfiss (shadow stack access) with CFI extension v0.4.0
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Make Zaamo + Zalrsc (Zba + Zbb + Zbs) imply A (B) in misa
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Assert misa.B bit through --isa=...B...
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The specification states that writes to read-only bits in a RW CSR are
ignored. The hstateen*[n] bits are read-only when mstateen*[n]=0. This
PR proposes ignoring writes to read-only hstateen*[n] bits when
mstateen*[n]=0 instead of writing the bits to 0.
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1. Add EXT_ZICFISS for enable Zicfiss with zicfiss extension name.
2. Add new software exception with tval 3 for shadow stack.
3. Implement sspush_x1/sspush_x5/sspopchk_x1/sspopchk_x5/ssrdp/ssamoswap_w/ssamoswap_d.
4. Implement c_sspush_x1/c_sspopchk_x5 in c_lui.h which has same encoding.
5. Add new special access type ss_access in xlate_flags_t for checking special read/write permission in SS(Shadow Stack) page.
6. Add new ss_load/ss_store/ssamoswap to enable ss_access flag.
7. Check special pte(xwr=010) of SS page.
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Interaction: Support until-mem operation on physical memory space
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Ignore writes to henvcfg fields (PBMTE, STCE, and ADUE) when read-only 0
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The henvcfg fields, i.e., PBMTE, STCE, and ADUE, are read-only 0 when
the corresponding bits in menvcfg are 0. Besides the reading behavior,
the spec also specified the writing behavior, i.e., ignoring writes.
This commit ignores writes to the henvcfg fields when read-only 0.
Reference: https://github.com/riscv/riscv-isa-manual/issues/1312
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Narrow scontext.data length to 32
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The commit provdes the change between debug spec 1.0.0-rc1 and 1.0.0-rc2
Reference: https://github.com/riscv/riscv-debug-spec/pull/981
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Implement syscall readlinkat
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Allow software check exception to be delegated from M mode regardless of Zicfilp being enabled
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Zicfilp being enabled
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Support Zicfilp
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Update vcompress.vm to not write vstart with 0 upon completion
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Vmcompress.vm requires vstart==0, so writing vstart with 0 is redundant.
To do this, spin off VI_LOOP_END_BASE from VI_LOOP_END. VI_LOOP_END
will contain VI_LOOP_END_BASE as well as a write of 0 to vstart.
See #1623 for full discussion.
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workaround to support custom extensions that use standard prefixes
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RISC-V ISA states (21.1):
"A standard-compatible global encoding can also use standard prefixes
for non-standard extensions if the associated standard extensions are
not included in the global encoding."
Currently all the instructions (either from standard or custom
extensions) are all being inserted into a single std::vector which is
then being sorted. An instruction matching process performs linear
search on that vector. The problem is that when a custom extension uses
the same opcode as standard one (i.e. match and mask are equal to the
standard counterparts) it is undefined which instruction will be picked.
That is because in std::sort "The order of equal elements is not
guaranteed to be preserved". That being said it is impossible to define
custom extension (via customext) that would use the prefix of a disabled
standard extension.
In this change I separate custom and standard extensions in two separate
std::vector's. By default we report an error if they have common
elements (There're an additional processor_t constructor's argument that
skips this check). If this error is disabled during instruction matching
we first trying to find it among custom instructions. If it has been
found the search is stopped and custom instruction is executed,
otherwise we look for it among standard instructions. Overall this
change does not completely fix the problem but at least makes it
possible to use the feature of RISC-V ISA.
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