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2021-07-29Enable precompiled headers when using clangtestAndrew Waterman4-3/+136
2021-07-29Significantly speed up compilation of disassemblerAndrew Waterman2-265/+373
Factor out most common instruction patterns into functions, so tha much less static code needs to be compiled.
2021-07-28Add NORETURN macroAndrew Waterman1-2/+4
2021-07-28Inline execute_insnAndrew Waterman1-1/+1
2021-07-28Significantly speed up compilation with GCCAndrew Waterman6-11/+1
Precompiled headers were broken because they weren't compiled with the same -fPIC setting as the rest of the code. Fix by just making everything use -fPIC.
2021-07-28Update disassembly to reflect renamed vector instructionsAndrew Waterman1-5/+5
2021-07-28Update encoding.hAndrew Waterman1-146/+168
2021-07-28Merge pull request #759 from ben-marshall/scalar-cryptoAndrew Waterman7-46/+11
Scalar crypto: post arch review updates
2021-07-28scalar-crypto: Remove remaining RV*_ONLY codeBen Marshall2-17/+3
- Remove remaining code which allowed spike to differentiate between RV32 and RV64 instructions which share an encoding. On branch scalar-crypto Changes to be committed: modified: disasm/disasm.cc modified: riscv/processor.cc
2021-07-28scalar-crypto: Remove DECLARE_RV*_ONLY macros from encoding.hBen Marshall1-21/+0
- These are no longer needed since none of the scalar crypto instructions overlap their encodings any more. - There is more code to be removed in relation to letting Spike handle overlapped RV32/64 instructions, but this will be done in subsequent commits and PRs so that the downstream scalar-crypto work can be un-gated. On branch scalar-crypto Changes to be committed: modified: riscv/encoding.h
2021-07-28scalar-crypto: Fix sign extension for SM3/SM4 instrsBen Marshall4-4/+4
On branch scalar-crypto Changes to be committed: modified: riscv/insns/sm3p0.h modified: riscv/insns/sm3p1.h modified: riscv/insns/sm4ed.h modified: riscv/insns/sm4ks.h
2021-07-28scalar-crypto: AES32 encoding changes post arch-reviewBen Marshall1-4/+4
- AES32 encodings nolonger overlap AES64 encodings On branch scalar-crypto Changes to be committed: modified: riscv/encoding.h
2021-07-28Merge pull request #755 from marcfedorow/rvpChunPing Chung7-3/+10
rvp: Fixed rv32 legality issues.
2021-07-27Required P-ext for SMAL insn.Mark Fedorov1-0/+1
2021-07-26Fix several bugs in P-extension register-pair handlingAndrew Waterman1-9/+7
- Words shouldn't be swapped based on enddianness; the lower-numbered register always holds the low-order bits. - Check for alignment, which also fixes a buffer overflow. - Handle x0 correctly: read as zero, discard writes.
2021-07-26Fixed rv32 legality issues.Mark Fedorov6-3/+9
2021-07-26Merge pull request #754 from chihminchao/clean-vqmac-vdotAndrew Waterman2-97/+0
decode: op: remove quad related macro and define
2021-07-26decode: op: remove quad related macro and defineChih-Min Chao2-97/+0
Let git keep the legacy code Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2021-07-22Merge branch 'daniellustig-nonleaf_dau'Andrew Waterman1-0/+4
2021-07-22Non-leaf PTEs with D/A/U==1 are reservedAndrew Waterman1-0/+2
Continuation of 80be4e21c3af7fe2966788ce538d3e3c3b0d60e3
2021-07-22Merge branch 'nonleaf_dau' of https://github.com/daniellustig/riscv-isa-sim ↵Andrew Waterman1-0/+2
into daniellustig-nonleaf_dau
2021-07-22Merge pull request #751 from riscv/fix-hlvxAndrew Waterman2-36/+28
Fix HLVX
2021-07-22Non-leaf PTEs with D/A/U==1 are reservedDan Lustig1-0/+2
...and hence should trigger page faults Thanks to @pdonahue-ventana for pointing this out: https://github.com/riscv/riscv-tests/issues/352
2021-07-21Fix hypervisor MXR and SUMAndrew Waterman2-10/+12
When V=1, vsstatus.MXR applies to the first stage of translation, and mstatus.MXR applies to both. mstatus.SUM doesn't apply when V=1, but vsstatus.SUM does.
2021-07-21Fix HLVX permissions checkAndrew Waterman2-20/+18
It should require X permissions, rather than (R || X).
2021-07-21Simplify (and possibly fix) handling of HLV/HSV TLB accessesAndrew Waterman2-14/+6
The previous scheme flushed the TLB before and after HLV/HSV. I think this was slightly wrong in the case of a debug trigger match: because the TLB gets refilled before the trigger exception gets thrown, we might not have reached the second TLB flush, so the entry could linger. Instead of flushing, simply don't access the TLB and don't refill the TLB for these instructions. Other than the trigger exception case, the effect is the same: we'll perform a full table walk and we won't cache the result.
2021-07-21HLV/HSV instructions should respect SPVP even in debug modeAndrew Waterman1-1/+1
2021-07-20Priv virtual memory updates (#750)Daniel Lustig10-4/+48
* Priv virtual memory updates * Priv 1.12 requires page faults when the address translation process reaches a PTE with any reserved bit set * Svpbmt uses two PTE bits, but otherwise has no effect on Spike (since Spike is sequentially consistent and does not model PMAs) * Add Svinval instructions Even though I updated riscv-opcodes separately, I merged the new defines into riscv/encoding.h manually, because riscv-opcodes seems to be a step ahead of riscv-isa-sim for a few vector opcodes, causing conflicts when regenerating encoding.h... If that gets fixed, and encoding.h gets regenerated automatically, I can remove it from this PR to avoid conflicts. * Svinval: use #include rather than copying code ..for the Svinval functions that are implemented in ways that just mimic SFENCE/HFENCE instructions Thanks to @aswaterman for the suggestion
2021-07-18Merge pull request #749 from chihminchao/ext-h-handle-mislaigned-in-guestAndrew Waterman4-27/+27
ext-h: handle mislaigned in guest
2021-07-17commitlog: add toggle for wfiChih-Min Chao1-1/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2021-07-17ext-h: handle mis-aligned exception for guest worldChih-Min Chao3-26/+24
It has been discussed that mis-aligned exception needs to update mstata.GVA ref: https://github.com/riscv/riscv-isa-manual/issues/673 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2021-07-16Fix MPRV-related bugAndrew Waterman1-1/+5
The wrong instruction might've been fetched when the PC was on the same page as a load or store used within the MPRV sequence. Fix by not using TLB within MPRV sequences. Resolves #746
2021-07-13Fix possible HLVX.WU bug (#744)Andrew Waterman1-1/+1
Need to sign extend result for RV32. Possible fix to #743
2021-07-09rvk: Sign-extension for aes32 insns (#742)marcfedorow4-4/+4
2021-07-08Fixed range issues on sr<al>[i]32.u insns (see #695) (#740)marcfedorow4-4/+4
2021-07-08Sgn-extension for Krypto insns. (See: #682) (#739)marcfedorow4-4/+4
2021-06-27fix(aes64ks1i) : fix note in riscv/insns/aes64ks1i.h (#733)Lu_Reaper1-1/+1
Co-authored-by: luruibo <dingiso.oah@gmail.com>
2021-06-14Merge pull request #658 from scottj97/hyper-disableAndrew Waterman1-12/+19
Fix disabling hypervisor via misa
2021-06-12Revert the redundant check for lr instruction (#728)sven3-6/+3
Co-authored-by: zhongchengyong <zhongcy93@gmail.com>
2021-06-09Apply scounteren only if S-mode is supported (#726)Shay Aviv1-1/+1
When U-mode is enabled but S-mode is disabled, `mcounteren` should control the availability of the hardware performance-monitoring counters in U-mode, and `scounteren` should be ignored. The current implementation (incorrectly) raises an illegal instruction trap when reading performance-monitoring counters in U-mode while S-mode is disabled, even if the counters are enabled in `mcounteren`.
2021-06-07PTE N bit moved from bit 62 to bit 63 (#724)Daniel Lustig1-1/+1
2021-06-06fix typo. (#723)Jiuyang Liu1-1/+1
2021-06-04Merge pull request #722 from ben-marshall/scalar-crypto-v0.9.2Andrew Waterman7-22/+12
scalar-crypto: Encoding fixes for v0.9.2
2021-06-04scalar-crypto: Encoding fixes for v0.9.2Ben Marshall7-22/+12
- Reverts the AES32 and SM4 instruction encodings back to a normal R-type encoding, per the advice of the architecture reviewers. On branch scalar-crypto-v0.9.2 Changes to be committed: modified: riscv/encoding.h modified: riscv/insns/aes32dsi.h modified: riscv/insns/aes32dsmi.h modified: riscv/insns/aes32esi.h modified: riscv/insns/aes32esmi.h modified: riscv/insns/sm4ed.h modified: riscv/insns/sm4ks.h
2021-06-04Merge pull request #699 from chihminchao/misc-fix-2021-04-21Andrew Waterman15-56/+41
Misc fix 2021 04 21
2021-06-04rvv: vdot has been removedChih-Min Chao5-27/+0
They have been remove in 0.10 spec Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2021-06-04encoding: udpate and move platform-related define outChih-Min Chao7-8/+17
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2021-06-02sim: fix multiple x extension issueChih-Min Chao1-1/+1
allow --isa=rv32gc_xdummy_xabcd_xdef Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2021-06-02sim: rewrite memory-region overlapping helperChih-Min Chao1-20/+19
problem: when the following memory region is specified -m0x00410000:0x1000, 0x00410200:0x1000, 0x00410400:0x1000, 0x00410600:0x1000, 0x00410800:0x1000, 0x00411000:0x1000, 0x00412000:0x1000, 0x00413000:0x1000, 0x00414000:0x1000 The error is ERROR (duplicate_node_names): Duplicate node name /memory@410 ERROR (duplicate_node_names): Duplicate node name /memory@410 ERROR (duplicate_node_names): Duplicate node name /memory@410 ERROR (duplicate_node_names): Duplicate node name /memory@410 ERROR (duplicate_node_names): Duplicate node name /memory@410 ERROR (duplicate_node_names): Duplicate node name /memory@410 ERROR: Input tree has errors, aborting (use -f to force output) cause: the merge_overlapping_memory_regions works not well in partial overlap case change: 1. use forward way to avoid weird reverse iterator behavior in C++ 2. use address but not page number since the base addresses are all aligned in make_mems Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2021-06-02pmp: mstatus.mprv should be clear if mpp is not M-modeChih-Min Chao2-0/+4
After the privilege draft-20191120-569d071, the section 3.1.6.3 says "An MRET or SRET instruction that changes the privilege mode to a mode less privileged than M also sets MPRV=0. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
generated by cgit v1.1 at 2024-08-16 02:03:56 +0000