Age | Commit message (Collapse) | Author | Files | Lines | |
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2023-01-04 | triggers: refactor: add bool itrigger_t::simple_match() | YenHaoChen | 2 | -1/+7 | |
2023-01-03 | Make misa.C read-only | Andrew Waterman | 1 | -6/+1 | |
This resolves the issue discussed in #1201. Prior to 0adf9307, clearing misa.C would disable compressed instructions and increase IALIGN to 32. Afterwards, clearing misa.C had essentially no effect because Zca and friends would stay enabled. While AFAICS this isn't technically incorrect, it certainly doesn't follow the principle of least surprise. Instead, remove the feature to toggle misa.C. The effect is that misa.C is 1 iff C is included in the ISA string, and IALIGN is independent of misa.C: specifically, IALIGN is 16 iff Zca is present. (And of course C implies Zca.) Removing the alignment check on misa writes is not a separate commit because these two changes should be made atomically. Not checking the alignment on misa writes goes hand-in-hand with misa.C being read-only. | |||||
2023-01-03 | Merge pull request #1205 from riscv-software-src/reservable | Andrew Waterman | 5 | -44/+50 | |
Add method to probe which memory regions are reservable | |||||
2023-01-03 | Support pte load/store from mmio regions | Jerry Zhao | 1 | -2/+2 | |
2023-01-03 | Pull pte load/store into methods of mmu_t | Jerry Zhao | 2 | -18/+54 | |
2023-01-03 | Add method to probe which memory regions are reservable | Jerry Zhao | 3 | -7/+13 | |
Default reservable regions is the same as before | |||||
2023-01-03 | Remove extraneous semicolon from simif.h | Jerry Zhao | 1 | -1/+1 | |
2023-01-03 | Specify addresses are physical for simif_t member functions | Jerry Zhao | 5 | -37/+37 | |
2023-01-02 | Merge pull request #1177 from YenHaoChen/pr-mcontrol6 | Scott Johnson | 3 | -59/+106 | |
Support mcontrol6 trigger | |||||
2022-12-29 | Make obvious that PC alignment mask is a function of IALIGN | Andrew Waterman | 1 | -1/+2 | |
No functional change. | |||||
2022-12-29 | Merge pull request #1197 from riscv-software-src/wfi | Andrew Waterman | 3 | -0/+10 | |
Prevent processor_t from retiring instructions after a WFI | |||||
2022-12-27 | Prevent processor_t from retiring instructions after a WFI | Jerry Zhao | 3 | -0/+10 | |
2022-12-27 | Merge pull request #1196 from riscv-software-src/readme_address | Andrew Waterman | 1 | -3/+3 | |
Change address used in gdb debug example. | |||||
2022-12-27 | Change address used in gdb debug example. | Tim Newsome | 1 | -3/+3 | |
PR #889 put a UART at 0x10000000, which conflicts with the old address. Fixes #1179. | |||||
2022-12-24 | Merge pull request #1195 from riscv-software-src/mmio_type | Andrew Waterman | 3 | -1/+11 | |
Expose access type in simif_t mmio_load interface | |||||
2022-12-23 | Merge pull request #1194 from riscv-software-src/clean-up-makefiles | Andrew Waterman | 6 | -57/+1 | |
Remove dead code in Makefiles | |||||
2022-12-23 | Add mmio_fetch to simif_t to distinguish between fetch/load for mmio accesses | Jerry Zhao | 3 | -1/+11 | |
2022-12-22 | Remove dead code in Makefile.in | Andrew Waterman | 1 | -3/+0 | |
2022-12-22 | Remove non-installed header lists from Makefile fragments | Andrew Waterman | 6 | -54/+1 | |
It's just dead code. (Dependences on headers are auto-generated as `.d` files.) | |||||
2022-12-21 | Merge pull request #1192 from riscv-software-src/improve-histogram | Andrew Waterman | 2 | -3/+7 | |
Slightly improve histogram feature | |||||
2022-12-21 | Merge pull request #1191 from riscv-software-src/always_histogram | Andrew Waterman | 5 | -37/+7 | |
Support histogram feature without configure option | |||||
2022-12-21 | Merge pull request #1147 from riscv-software-src/extension-namespace | Andrew Waterman | 1 | -1/+1 | |
Support more than 65 Z* extensions | |||||
2022-12-21 | Merge pull request #1193 from riscv-software-src/fix-build-nondeterminism | Andrew Waterman | 1 | -0/+1 | |
Fix build nondeterminism by deleting archives before recreating | |||||
2022-12-21 | Fix build nondeterminism by deleting archives before recreating | Andrew Waterman | 1 | -0/+1 | |
Otherwise, `ar rcs` will add to the previous archive, creating the possibility of multiple functions with the same name in the archive. The linker might not choose the most recent version, resulting in undefined behavior. | |||||
2022-12-21 | Speed up histogramming by changing data structure | Andrew Waterman | 1 | -1/+1 | |
Since we no longer rely on the map's order, use unordered_map. | |||||
2022-12-21 | Sort histogram printout count, rather than address | Andrew Waterman | 1 | -2/+6 | |
2022-12-21 | Remove --enable-histogram option | Andrew Waterman | 4 | -29/+0 | |
It's now redundant. | |||||
2022-12-21 | Only clear logging structures if logging is enabled | Andrew Waterman | 1 | -2/+5 | |
This speeds up histogramming when logging is disabled, with almost no slowdown for the logging case. | |||||
2022-12-21 | Always use slow path for histogramming | Andrew Waterman | 1 | -2/+2 | |
Speeds up fast path after unconditionally enabling histogram. | |||||
2022-12-21 | Support histogram regardless of configure flag | Andrew Waterman | 2 | -4/+0 | |
2022-12-20 | Merge pull request #1190 from riscv-software-src/reduce-compile-time | Andrew Waterman | 6 | -44/+72 | |
Reduce compile time increase introduced by #1189 | |||||
2022-12-20 | Reduce compile time increase introduced by #1189 | Andrew Waterman | 6 | -44/+72 | |
Generate one object file per instruction rather than two, which reduces the overhead of invoking the compiler so many times. This also reduces the size of the (unstripped) binary substantially. | |||||
2022-12-21 | triggers: add mcontrol6 trigger | YenHaoChen | 3 | -1/+53 | |
2022-12-21 | triggers: refactor: add mcontrol_common_t::legalize_match() function | YenHaoChen | 2 | -14/+17 | |
2022-12-21 | triggers: refactor: remove redundant namespace qualifiers | YenHaoChen | 1 | -7/+7 | |
2022-12-21 | triggers: refactor: extract mcontrol_common_t from mcontrol_t | YenHaoChen | 2 | -6/+10 | |
2022-12-21 | triggers: refactor: update trigger_t::mode_match() | YenHaoChen | 1 | -5/+5 | |
2022-12-21 | triggers: refactor: add trigger_t::mode_match() function | YenHaoChen | 2 | -14/+14 | |
2022-12-20 | Support more than 65 Z* extensions | Andrew Waterman | 1 | -1/+1 | |
The isa_extension_t enum already has 44 extensions. In not too long, the enum will grow in size to 65, when it will collide with the 'A' extension. Fix that preemptively by starting after 'Z'. This approach will run out of steam at 165 extensions because we are using `unsigned char` to represent extensions, but opefully we will have retired by that point. In seriousness, we will probably need to refactor the extension_enabled logic at some point in the future (e.g. when the configuration structure is finally added) and at that point we should lift the `char` limit. | |||||
2022-12-21 | triggers: refactor: move m/s/u/vs/vu to trigger_t | YenHaoChen | 1 | -15/+6 | |
2022-12-21 | triggers: refactor: add mcontrol.vs and mcontrol.vu | YenHaoChen | 2 | -3/+4 | |
2022-12-21 | triggers: refactor: cleaner vs and vu checking | YenHaoChen | 1 | -8/+4 | |
2022-12-20 | Merge pull request #1189 from riscv-software-src/always_commitlog | Andrew Waterman | 17 | -129/+112 | |
Always support commit-logging without performance penalty | |||||
2022-12-20 | Always build with commit logging support | Jerry Zhao | 6 | -37/+3 | |
2022-12-20 | Add logged instruction variants to insn_desc_t | Jerry Zhao | 4 | -20/+49 | |
2022-12-20 | Add logged variants of insn templates | Jerry Zhao | 6 | -18/+36 | |
2022-12-20 | Replace compile-time commitlog check with runtime check for vector writes | Jerry Zhao | 1 | -3/+1 | |
2022-12-20 | Replace compile-time conditional with run-time conditional for load/store ↵ | Jerry Zhao | 1 | -19/+4 | |
logging | |||||
2022-12-20 | Split execute_insn into fast and logged variants | Jerry Zhao | 1 | -14/+9 | |
Fast variant should only be used when logging is disabled | |||||
2022-12-20 | Force slow-path when commit-logging is enabled | Jerry Zhao | 1 | -1/+1 | |