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2023-02-04Contain C/Zc*-enable logic entirely within misa_csr_tplctlab-plct-zce-fix2Andrew Waterman2-21/+10
For DRY purposes, processor_t::set_extension_enable checks isa_t::extension_enabled, rather than relying on the caller to do so.
2023-02-03Make Zca changeable if C is supported in isa string and Zcb/Zcmt/Zcmp are ↵Weiwei Li2-2/+14
not supported Restore misa.C writable and disable/enable Zca(if changeable) when clear/set misa.C Increase IALIGN only when misa.C is cleared and Zca is changeable (Zca will be disabled)
2023-02-03Maintain a changeable list for multi-letter extensions in extension_changeableWeiwei Li2-2/+18
function (Only the extensions supported in isa string can be truly changeable) Add Zcf/Zcd to the changeable list: disable them when misa.F/D is cleared or Zca is disabled, enable them when misa.F/D is set and Zca is enabled
2023-02-03Maintain extension_enable_table in each processor separatelyWeiwei Li3-2/+8
2023-02-02Merge pull request #1242 from riscv-software-src/publichtifAndrew Waterman1-3/+3
Make htif->get_to/fromhost_addr methods public
2023-02-02Make htif->get_to/fromhost_addr methods publicJerry Zhao1-3/+3
2023-01-31Merge pull request #1241 from riscv-software-src/zicondAndrew Waterman6-2/+93
Implement Zicond (conditional integer operations)
2023-01-31Zicond: implement Zicond (conditional integer operations)Philipp Tomsich5-0/+12
This implements the Zicond (conditional integer operations) extension, as of version 1.0-draft-20230120. The Zicond extension acts as a building block for branchless sequences including conditional-arithmetic, conditional-logic and conditional-select/move. The following instructions constitute Zicond: - czero.eqz rd, rs1, rs2 => rd = (rs2 == 0) ? 0 : rs1 - czero.nez rd, rs1, rs2 => rd = (rs2 != 0) ? 0 : rs1 See https://github.com/riscv/riscv-zicond/releases/download/v1.0-draft-20230120/riscv-zicond_1.0-draft-20230120.pdf for the proposed specification and usage details.
2023-01-31Update encoding.h for Zicond opcodesAndrew Waterman1-2/+81
Note this encoding.h's history is unusual because riscv-opcodes master is currently incompatible with Spike. See the PR that contains its commit hash (https://github.com/riscv/riscv-opcodes/pull/157) and discussion at https://github.com/riscv-software-src/riscv-isa-sim/pull/1234#discussion_r1092243338
2023-01-30Merge pull request #1220 from YenHaoChen/pr-icountScott Johnson6-10/+130
Add icount trigger
2023-01-30triggers: optimize icount_t::icount_check_needed()YenHaoChen1-1/+1
2023-01-30triggers: update README.md: add icount triggerYenHaoChen1-1/+1
2023-01-30triggers: add detect_icount_match()YenHaoChen3-6/+65
2023-01-30triggers: force to slow path with icount triggersYenHaoChen4-2/+9
2023-01-30triggers: add icount_t and update tinfoYenHaoChen2-0/+52
2023-01-30triggers: if match triggers with both breakpoint exception and entering ↵YenHaoChen1-6/+8
D-mode, then enter D-mode and ignore breakpoint exception
2023-01-30triggers: refactor: use CSR_TDATA1_TYPE_MCONTROL6 instead of number 6YenHaoChen1-1/+1
2023-01-27Merge pull request #1240 from adurbin-rivos/svaduAndrew Waterman11-15/+17
Add support for Svadu Extension
2023-01-27Remove dirty_enabled from cfg_tAaron Durbin5-8/+0
The addition of Svadu support and removal of --mmu-dirty command line flag results in the dirty_enabled configuration state no longer being used. Remove the remnants of this state.
2023-01-27Remove --mmu-dirty command line flagAaron Durbin1-2/+0
With the addition of Svadu support, the --mmu-dirty flag no longer controls behavior of A/D updates to PTEs. Remove the flag.
2023-01-27Use Svadu control bits to drive A/D updatesAaron Durbin1-2/+4
The Svadu (https://github.com/riscv/riscv-svadu) extension updates the A/D bits of PTEs: 1. In S/HS mode when menvcfg.hade=1 2. In G-stage page tables when menvcfg.hade=1 3. In VS mode when henvcfg.hade=1 To enable this behavior the 'svadu' ISA string is needed. This newly added behavior supplants the --mmu-dirty flag. However, that flag is not yet removed.
2023-01-27Enable Svadu control bits in menvcfg and henvcfgAaron Durbin2-1/+4
Add in the support for the HADE fields in menvcfg and henvcfg based off of the svadu ISA string. This only allows for the writable HADE bits being exposed when the svadu ISA string is employed. No other behavior is implemented.
2023-01-27Add Svadu CSR bit definitionsAaron Durbin1-2/+6
The Svadu extension adds a HADE field (bit 61) to both menvcfg and henvcfg. Add the definitions so they can be utilized.
2023-01-27Add Svadu Extension Parsing to ISA ParserAaron Durbin2-0/+3
Make the ISA parser understand the Svadu extension.
2023-01-20Merge pull request #1233 from riscv-software-src/pmp64Andrew Waterman3-18/+9
Support all 64 PMP regions
2023-01-19Improve PMP number/granularity error messagesAndrew Waterman1-3/+4
2023-01-19Perform pmpregions input validation in only one placeAndrew Waterman1-14/+4
No reason to check it both in sim_t::sim_t and in processor_t::set_pmp_num.
2023-01-19Support all 64 PMP registersAndrew Waterman1-1/+1
2023-01-19Merge pull request #1219 from riscv-software-src/ntriggersAndrew Waterman7-14/+26
Add --triggers=n to control the number of supported triggers
2023-01-18Add --triggers flag to select number of triggersJerry Zhao1-0/+2
2023-01-18Instantiate tdata/tinfo as const csrs when trigger_count == 0Jerry Zhao3-8/+12
2023-01-18Add trigger_count field to cfg_tJerry Zhao5-6/+12
2023-01-17Merge pull request #1232 from riscv-software-src/jerryz123-patch-1Andrew Waterman1-0/+3
Add htif_t tohost/fromhost accessors
2023-01-17Add htif_t tohost/fromhost accessorsJerry Zhao1-0/+3
Signed-off-by: Jerry Zhao <jerryz123@berkeley.edu>
2023-01-16Merge pull request #1230 from gr816ox/patch-2Andrew Waterman1-0/+6
Add more hint when searched path is wrong
2023-01-16Add more hint when searched path is wrong gr816ox1-0/+6
Delete the old branch and pull a new one, because of a wrong force push. Git is not as easy as I think. Signed-off-by: gr816ox <50945677+gr816ox@users.noreply.github.com>
2023-01-14Merge pull request #1228 from riscv-software-src/ext-limitAndrew Waterman3-29/+31
Lift artificial limit of 191 extensions; simplify isa_parser_t::extension_enabled
2023-01-13Simplify isa_parser_t::extension_enabledAndrew Waterman1-4/+1
Now that we guarantee that max_isa and extension_table are synchronized, we only need to check the latter.
2023-01-13Keep max_isa and extension_table in sync in exactly one placeAndrew Waterman1-22/+18
This fixes a bug where --isa=rv64imafdc would fail to set extension_table['F'] because of the ad hoc manner in which we were synchronizing max_isa and extension_table.
2023-01-13Use more appropriate data structure for extension_tableAndrew Waterman2-3/+2
We know its size at compile time.
2023-01-13Lift artificial limit of 191 extensionsAndrew Waterman3-1/+11
Add new accessors that accept the isa_extension_t enum. Retain the original ones that accept unsigned char to avoid churn.
2023-01-13Merge pull request #1214 from YenHaoChen/pr-legalize-timingScott Johnson2-16/+22
Add legalize_timing() for tdata1.timing
2023-01-13triggers: refactor: use static and remove const for legalize_action()YenHaoChen2-2/+2
Since this method does not use 'this', we turn this method into static.
2023-01-13triggers: refactor: use static and remove const for legalize_match()YenHaoChen2-2/+2
Since this method no longer use 'this', we turn this method into static.
2023-01-13triggers: refactor: remove legalization_action()'s dependency on dmodeYenHaoChen2-7/+8
avoid breaking functionality by reordering statements in tdata1.write()
2023-01-13triggers: legalize timing=1(after) for load data triggerYenHaoChen2-4/+7
As recommended in the debug spec table "Suggested Trigger Timings", to avoid the footgun of replaying a load (which may have side effects) when the breakpoint trap handler returns. reference: https://github.com/riscv-software-src/riscv-isa-sim/pull/1208#issuecomment-1373035906 ----------------------------------------------------------------------- The legalize_timing() depends on select, execution, load, and store, which are updated in the same function tdata1_write(). As a result, reordering statements in the tdata1_write() may break the functionality. Passing those variables as parameters to legalize_timing() does not solve the problem. Thus, we give the original write value and the masks of the variables to the legalize_timing(). This makes the legalization function independent of the updating variables and resolves the issue. reference: https://github.com/riscv-software-src/riscv-isa-sim/pull/1214
2023-01-12Merge pull request #1225 from riscv-software-src/no-threadsAndrew Waterman2-31/+14
Run Spike and HTIF in a single thread, rather than two
2023-01-12Merge pull request #1224 from riscv-software-src/uart-poll-less-oftenAndrew Waterman2-1/+12
For NS16550 UART, poll stdin less often
2023-01-12triggers: refactor: remove an outdated commentYenHaoChen1-1/+0
2023-01-12triggers: refactor: add mcontrol_common_t::legalize_timing() functionYenHaoChen2-6/+9
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