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2022-11-15Use ACTION_DEBUG_MODE instead of 1itrigger-etrigger-cleanupYenHaoChen1-1/+1
Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com>
2022-11-15Update riscv/triggers.ccYenHaoChen1-1/+1
Co-authored-by: Tim Newsome <tim@sifive.com> Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com>
2022-11-15fix compilation error: unused parameterYenHaoChen2-4/+4
2022-11-15check itrigger/etrigger after taking trapYenHaoChen1-1/+6
2022-11-15add take_trigger_action() to processor.h/processor.ccYenHaoChen3-12/+25
2022-11-15update module_tYenHaoChen2-31/+82
2022-11-15add itrigger_t and etrigger_tYenHaoChen2-1/+153
2022-11-15update debug_defines.hYenHaoChen1-892/+1432
2022-11-15add disabled_trigger_t to triggersYenHaoChen2-0/+27
2022-11-15trigger_t: Protect destructor and memory_access_match()Tim Newsome1-7/+3
2022-11-15triggers: Move trigger_t.hit to mcontrol_t.hitTim Newsome1-2/+1
2022-11-15triggers: Access action bit through get_action()Tim Newsome2-2/+4
2022-11-15triggers: rename chainTim Newsome2-8/+8
chain() -> get_chain() chain_bit -> chain
2022-11-15triggers: Rename/move dmodeTim Newsome2-5/+7
dmode() -> get_dmode() trigger_t.dmode_bit -> mcontrol_t.dmode
2022-11-15triggers: rename storeTim Newsome3-7/+7
store() -> get_store() store_bit -> store
2022-11-15Triggers: rename loadTim Newsome3-7/+7
load() -> get_load() load_bit -> bit
2022-11-15Triggers rename executeTim Newsome3-8/+8
execute() -> get_execute(), execute_bit -> execute
2022-11-15Move tdata2 from mcontrol_t into its own class.YenHaoChen2-16/+22
structuralize trigger's tdata CSRs for modularization
2022-10-20Merge pull request #1122 from riscv-software-src/more-mmu-simplificationAndrew Waterman71-219/+190
Fix minor MMU bugs; clean up MMU some more
2022-10-20Merge pull request #1125 from riscv-software-src/cbo-fixesAndrew Waterman2-6/+8
Fix tval reporting for CBOs; constrain cache-block sizes to reasonable values
2022-10-20Use reg_t, not uint64_t, for address-like quantitiesAndrew Waterman1-2/+2
2022-10-20Fix tval reporting for CBOsAndrew Waterman1-2/+1
mmu_t::translate may raise exceptions and so must be called with the original virtual address for tval to be set correctly.
2022-10-20Set 16..4096-byte bound on cache-block sizeAndrew Waterman1-2/+5
16 B suffices to subsume all aligned accesses (including the Q extension). Spike does not actually rely on this property, but in some real systems, it is impractical to guarantee atomicity across cache lines. 4096 B suffices to prevent cache lines from spanning pages (which would require multiple TLB accesses). This one is a bug fix, since we were not performing multiple TLB accesses in this case.
2022-10-20move fucntion cto() from processor.h to arith.hYenHaoChen3-9/+10
Only triggers.cc uses the arithmetic function cto(). Instead of putting the cto() in processor.h, putting it in arith.h with other arithmetic functions, e.g., ctz() and clz(), makes more sense.
2022-10-19Template-ize storesAndrew Waterman17-40/+30
2022-10-19Template-ize loadsAndrew Waterman22-54/+38
2022-10-19Template-ize AMOsAndrew Waterman20-34/+29
2022-10-19DRY in store-conditional instructionsAndrew Waterman3-12/+15
2022-10-19Simplify check_load_reservationAndrew Waterman1-2/+2
Invoking refill_tlb to get the physical address is somewhat baroque, and not even helpful in practice, since successful SCs will fill the TLB anyway.
2022-10-19Template-ize hypervisor loads and storesAndrew Waterman14-33/+28
2022-10-19Remove require_alignment flag from loadsAndrew Waterman2-7/+7
The last remaining use was LR, which we can identify through other means.
2022-10-19Fix imprecise exception on LR to MMIO spaceAndrew Waterman4-17/+14
The old implementation performed the load before checking whether the memory region was valid for LR. So, for LR to MMIO, we would action side effects before raising the exception, which is not precise.
2022-10-19Template-ize load_func macroAndrew Waterman1-15/+20
For now, preserve the macro for compatibility with existing uses.
2022-10-19Template-ize store_func macroAndrew Waterman1-14/+18
For now, preserve the macro for compatibility with existing uses.
2022-10-19No need to require_alignment for the load part of the AMOAndrew Waterman1-1/+1
The earlier call to store_slow_path will catch the misalignment.
2022-10-19Remove actually_store and require_alignment parameters from store_func macroAndrew Waterman1-8/+6
These are now only used by AMOs. Since AMOs are relatively uncommon, and since the slow path really isn't slow anymore, send them down the slow path to simplify the common case.
2022-10-19remove duplicate CMO item in README.mdWeiwei Li1-1/+0
2022-10-19do memcpy only for actually_store in store_slow_path_intrapageWeiwei Li1-2/+4
2022-10-19Fix missing sentinel warning in dts.cc when using gnu++17 standardWeiwei Li1-1/+1
2022-10-19Fix forced linking when compiling headersbluew1-1/+1
2022-10-17fix clang buildAndrew Waterman1-1/+1
2022-10-17Add command to display privilege level in interactive modeJerry Zhao4-0/+32
2022-10-17Make PLIC/NS16550 coding style more conformantAndrew Waterman3-84/+61
2022-10-17Merge branch 'master' into plic_uart_v1plic_uart_v1Andrew Waterman229-6973/+8037
2022-10-16Add interactive mode commands to read clint mtime/mtimecmpJerry Zhao3-0/+27
2022-10-14Add dump memory command to interactive modeJerry Zhao4-0/+29
2022-10-14Support command-line configuration of number of pmpregionsJerry Zhao5-2/+10
2022-10-14Merge pull request #1114 from riscv-software-src/data_optionalScott Johnson4-21/+21
In triggers, use optional<data> instead of {has_data, data}
2022-10-14In triggers, use optional<data> instead of {has_data, data}Andrew Waterman4-16/+17
2022-10-14Report error if an unsupported memory configuration is detectedParshintsev Anatoly2-9/+18
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