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2020-07-31test_hetero_mcheterogeneous_mcUdit Khanna1-1/+3
2020-07-30Merge pull request #519 from chihminchao/rvv-pre-1.0Andrew Waterman64-282/+483
Rvv pre 1.0
2020-07-29f16: fix Nan-Box macroChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-29rvv: fix frac_lmul get functionChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-29rvv: remove isa string zvamoand zvlssegChih-Min Chao3-18/+0
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-29rvv: remove veew/vemul stateChih-Min Chao3-32/+25
They aren't arch state Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-29rvv: add vrgatherei16.vvChih-Min Chao4-13/+51
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-29rvv: add new whole reg load/store instructionsChih-Min Chao25-23/+212
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-29rvv: op: rearrange some instruction since generation order changeChih-Min Chao1-36/+36
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-29rvv: op: fix amo namingChih-Min Chao39-148/+148
The original name misses the 'i' in instruction mae vamoswape8 -> vamoswapei8 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-29rvv: remove slenChih-Min Chao2-8/+5
The command parser still can accept SLEN but the value is not stored in implementation Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-29rvv: initialize vector register as zeroChih-Min Chao1-1/+2
some dump and comparison tool may depennd the initial state of vector register. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-29rvv: disasm: fix missing vamoorei operandsChih-Min Chao1-1/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-28Merge pull request #517 from riscv/rvv-1.0-vtypeAndrew Waterman2-5/+4
Incorporate RVV 1.0 vtype layout change
2020-07-28Incorporate RVV 1.0 vtype layout changeAndrew Waterman2-5/+4
2020-07-21Remove deprecated decoding of xor x0,x0,x0Andrew Waterman1-1/+0
Some UCB implementations once used this to represent a pipeline bubble. But this encoding is reserved for future standard HINT use. Resolves #503
2020-07-16Fix legalize_privilege for extension H (#508)Abhinay Kayastha1-1/+1
2020-07-15commitlog: fix vmvnfr.v register information (#506)Chih-Min Chao1-4/+17
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-13rvv: fix viota.m dst and src overlapping rule (#504)Chih-Min Chao1-5/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-09Merge pull request #493 from avpatel/riscv-hyp-ext-v0.6.1Andrew Waterman35-146/+946
RISC-V H-Extension v0.6.1 Support
2020-07-09Add kernel command line option for spikeAnup Patel1-0/+18
It is very inconvenient to always embed kernel flat image into OpenSBI for booting Linux/Xvisor on Spike. We add optional "--kernel" command line option for spike. Using this new option, users can specify kernel flat image separately and OpenSBI ELF separately. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2020-07-09Add bootargs command-line option to SpikeAnup Patel5-8/+25
We add bootargs command-line option to Spike which allows us to provide custom kernel parameters to Linux and Xvisor. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2020-07-09Implement new instructions of hypervisor extensionAnup Patel16-0/+81
We add new HFENCE, HLV, and HSV instructions for HS-mode which are defined as part of the RISC-V hypervisor extension. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2020-07-09Implement hypervisor two-stage MMUAnup Patel2-51/+179
We extend our existing MMU implementation to support two-stage translation when running VS-mode for RISC-V hypervisor extension. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2020-07-09Implement hypervisor CSRs read/writeAnup Patel8-53/+502
We add newly defined hypervisor CSRs and allow M/HS-mode to access these CSRs. The MRET, SRET, ECALL and WFI instructions have also been updated so that virt-to-novirt switch and exception cause is based on HART virtualization state. Subsequent patches will implement two-stage page tables, HFENCE instructions and HSV/HLV instructions. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2020-07-08rvv: vstart register needs only lg2(VLEN) bits (#501)Chih-Min Chao1-1/+1
As section 3.6 says: The vstart CSR is defined to have only enough writable bits to hold the largest element index (one less than the maximum VLMAX) or lg2(VLEN) bits. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-08Extend trap classes to pass more informationAnup Patel7-28/+60
With hypervisor extension, we have more CSRs providing trap related information. We extend existing trap classes to pass additional trap information required by hypervisor extension. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2020-07-08Add hypervisor extension related CSR and instruction definesAnup Patel1-6/+81
We add missing CSR and instruction encoding related defines for hypervisor extension. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2020-07-07Merge pull request #500 from abhinay-kayastha/GetCsrZeroPmpUdit Khanna1-0/+3
If n_pmp=0, then pmp is not implemented hence raise trap
2020-07-06If n_pmp=0, then pmp is not implemented hence raise trapAbhinay Kayastha1-0/+3
2020-07-04Merge pull request #499 from chihminchao/commitlog-2020-07-02Andrew Waterman5-39/+142
Commitlog 2020 07 02
2020-07-02commitlog: support csr accessChih-Min Chao2-2/+99
For csr register access instructions, there are log like Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-02commitlog: simplify print_value pathChih-Min Chao1-26/+27
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-02commitlog: extend hint bit to record csr accessChih-Min Chao3-6/+12
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-02rvv: make vmvfnr respect vstartChih-Min Chao1-5/+4
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-06-25Merge pull request #494 from chihminchao/rvv-fix-2020-06-25Andrew Waterman2-4/+5
Rvv fix 2020 06 25
2020-06-25rvv: remove unecessary accessChih-Min Chao1-3/+0
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-06-25rvv: fix viota.m overlapping ruleChih-Min Chao1-1/+5
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-06-17Merge pull request #491 from chihminchao/rvv-fix-2020-06-18Andrew Waterman3-4/+4
Rvv fix 2020 06 18
2020-06-17rvv: make v[sl]1r respect vstartChih-Min Chao2-2/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-06-17rvv: commitlog: fix fractional lmul dumpChih-Min Chao1-2/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-06-16Merge pull request #490 from chihminchao/rvv-fix-2020-06-17Andrew Waterman3-1/+11
Rvv fix 2020 06 17
2020-06-16rvv: disasm: fix vwadd.wx operandChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-06-16zfh: support register dump in interactive modeChih-Min Chao2-0/+10
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-06-16Merge pull request #489 from chihminchao/extension-zfhAndrew Waterman40-1/+357
Extension zfh
2020-06-16ext: handle diaseembler initialization from --extensionChih-Min Chao1-0/+4
There are two options to specify custom extension and register it 1. --isa with x ex: --isa=rv64gcv_xmyext parse, load, register in processor_t::processor_t 2. --extension parse, load in main register later by calling processort_t::register_extension The patch fix the register pass in 2 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-06-16zfh: implement all instructionsChih-Min Chao37-1/+207
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-06-16zfh: disasm: add fp16 disasmChih-Min Chao1-0/+38
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-06-16zfh: op: add scalar opcodeChih-Min Chao1-0/+108
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-06-15remove the redundant code (#488)Dave Wen2-2/+1
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