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author | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2010-10-02 17:45:29 -0700 |
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committer | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2010-10-02 17:45:29 -0700 |
commit | fcdd030cbe07d48cbd442d207d53dc3947aff02c (patch) | |
tree | 6bf1257f637e7b4844234d050d6fa7b941fcba98 /riscv | |
parent | 04fa9f8603fb3034ca23e9c5a15716c6f95b7dfe (diff) | |
download | spike-fcdd030cbe07d48cbd442d207d53dc3947aff02c.zip spike-fcdd030cbe07d48cbd442d207d53dc3947aff02c.tar.gz spike-fcdd030cbe07d48cbd442d207d53dc3947aff02c.tar.bz2 |
[sim, xcc] changed cvt/trunc to use GPRs for int args
this way, we don't have to futz with storing integers in recoded
floating-point registers. too bad we lose some decoupling.
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/insns/cvt_d_l.h | 3 | ||||
-rw-r--r-- | riscv/insns/cvt_d_w.h | 2 | ||||
-rw-r--r-- | riscv/insns/cvt_s_l.h | 3 | ||||
-rw-r--r-- | riscv/insns/cvt_s_w.h | 2 | ||||
-rw-r--r-- | riscv/insns/cvtu_d_l.h | 3 | ||||
-rw-r--r-- | riscv/insns/cvtu_d_w.h | 2 | ||||
-rw-r--r-- | riscv/insns/cvtu_s_l.h | 3 | ||||
-rw-r--r-- | riscv/insns/cvtu_s_w.h | 2 | ||||
-rw-r--r-- | riscv/insns/trunc_l_d.h | 3 | ||||
-rw-r--r-- | riscv/insns/trunc_l_s.h | 3 | ||||
-rw-r--r-- | riscv/insns/trunc_w_d.h | 2 | ||||
-rw-r--r-- | riscv/insns/trunc_w_s.h | 2 | ||||
-rw-r--r-- | riscv/insns/truncu_l_d.h | 3 | ||||
-rw-r--r-- | riscv/insns/truncu_l_s.h | 3 | ||||
-rw-r--r-- | riscv/insns/truncu_w_d.h | 2 | ||||
-rw-r--r-- | riscv/insns/truncu_w_s.h | 2 |
16 files changed, 24 insertions, 16 deletions
diff --git a/riscv/insns/cvt_d_l.h b/riscv/insns/cvt_d_l.h index 5faac2a..8a60e64 100644 --- a/riscv/insns/cvt_d_l.h +++ b/riscv/insns/cvt_d_l.h @@ -1,3 +1,4 @@ +require64; require_fp; -FRDR = i64_to_f64(FRS1); +FRDR = i64_to_f64(RS1); set_fp_exceptions; diff --git a/riscv/insns/cvt_d_w.h b/riscv/insns/cvt_d_w.h index 67bc798..96acc2b 100644 --- a/riscv/insns/cvt_d_w.h +++ b/riscv/insns/cvt_d_w.h @@ -1,3 +1,3 @@ require_fp; -FRDR = i32_to_f64(FRS1); +FRDR = i32_to_f64(RS1); set_fp_exceptions; diff --git a/riscv/insns/cvt_s_l.h b/riscv/insns/cvt_s_l.h index f5332f9..fe10e85 100644 --- a/riscv/insns/cvt_s_l.h +++ b/riscv/insns/cvt_s_l.h @@ -1,3 +1,4 @@ +require64; require_fp; -FRDR = i64_to_f32(FRS1); +FRDR = i64_to_f32(RS1); set_fp_exceptions; diff --git a/riscv/insns/cvt_s_w.h b/riscv/insns/cvt_s_w.h index 9db5386..8501547 100644 --- a/riscv/insns/cvt_s_w.h +++ b/riscv/insns/cvt_s_w.h @@ -1,3 +1,3 @@ require_fp; -FRDR = i32_to_f32(FRS1); +FRDR = i32_to_f32(RS1); set_fp_exceptions; diff --git a/riscv/insns/cvtu_d_l.h b/riscv/insns/cvtu_d_l.h index 5faac2a..8a60e64 100644 --- a/riscv/insns/cvtu_d_l.h +++ b/riscv/insns/cvtu_d_l.h @@ -1,3 +1,4 @@ +require64; require_fp; -FRDR = i64_to_f64(FRS1); +FRDR = i64_to_f64(RS1); set_fp_exceptions; diff --git a/riscv/insns/cvtu_d_w.h b/riscv/insns/cvtu_d_w.h index 1b35e06..494f9b0 100644 --- a/riscv/insns/cvtu_d_w.h +++ b/riscv/insns/cvtu_d_w.h @@ -1,3 +1,3 @@ require_fp; -FRDR = ui32_to_f64(FRS1); +FRDR = ui32_to_f64(RS1); set_fp_exceptions; diff --git a/riscv/insns/cvtu_s_l.h b/riscv/insns/cvtu_s_l.h index f5332f9..fe10e85 100644 --- a/riscv/insns/cvtu_s_l.h +++ b/riscv/insns/cvtu_s_l.h @@ -1,3 +1,4 @@ +require64; require_fp; -FRDR = i64_to_f32(FRS1); +FRDR = i64_to_f32(RS1); set_fp_exceptions; diff --git a/riscv/insns/cvtu_s_w.h b/riscv/insns/cvtu_s_w.h index 252e0cc..fb76e6d 100644 --- a/riscv/insns/cvtu_s_w.h +++ b/riscv/insns/cvtu_s_w.h @@ -1,3 +1,3 @@ require_fp; -FRDR = ui32_to_f32(FRS1); +FRDR = ui32_to_f32(RS1); set_fp_exceptions; diff --git a/riscv/insns/trunc_l_d.h b/riscv/insns/trunc_l_d.h index e71957b..63af055 100644 --- a/riscv/insns/trunc_l_d.h +++ b/riscv/insns/trunc_l_d.h @@ -1,3 +1,4 @@ +require64; require_fp; -FRDR = f64_to_i64_r_minMag(FRS1,true); +RDR = f64_to_i64_r_minMag(FRS1,true); set_fp_exceptions; diff --git a/riscv/insns/trunc_l_s.h b/riscv/insns/trunc_l_s.h index 1d48192..03c114a 100644 --- a/riscv/insns/trunc_l_s.h +++ b/riscv/insns/trunc_l_s.h @@ -1,3 +1,4 @@ +require64; require_fp; -FRDR = f32_to_i64_r_minMag(FRS1,true); +RDR = f32_to_i64_r_minMag(FRS1,true); set_fp_exceptions; diff --git a/riscv/insns/trunc_w_d.h b/riscv/insns/trunc_w_d.h index 2fea3dc..5f874aa 100644 --- a/riscv/insns/trunc_w_d.h +++ b/riscv/insns/trunc_w_d.h @@ -1,3 +1,3 @@ require_fp; -FRDR = f64_to_i32_r_minMag(FRS1,true); +RDR = f64_to_i32_r_minMag(FRS1,true); set_fp_exceptions; diff --git a/riscv/insns/trunc_w_s.h b/riscv/insns/trunc_w_s.h index e70f9c4..42be753 100644 --- a/riscv/insns/trunc_w_s.h +++ b/riscv/insns/trunc_w_s.h @@ -1,3 +1,3 @@ require_fp; -FRDR = f32_to_i32_r_minMag(FRS1,true); +RDR = f32_to_i32_r_minMag(FRS1,true); set_fp_exceptions; diff --git a/riscv/insns/truncu_l_d.h b/riscv/insns/truncu_l_d.h index e71957b..63af055 100644 --- a/riscv/insns/truncu_l_d.h +++ b/riscv/insns/truncu_l_d.h @@ -1,3 +1,4 @@ +require64; require_fp; -FRDR = f64_to_i64_r_minMag(FRS1,true); +RDR = f64_to_i64_r_minMag(FRS1,true); set_fp_exceptions; diff --git a/riscv/insns/truncu_l_s.h b/riscv/insns/truncu_l_s.h index 1d48192..03c114a 100644 --- a/riscv/insns/truncu_l_s.h +++ b/riscv/insns/truncu_l_s.h @@ -1,3 +1,4 @@ +require64; require_fp; -FRDR = f32_to_i64_r_minMag(FRS1,true); +RDR = f32_to_i64_r_minMag(FRS1,true); set_fp_exceptions; diff --git a/riscv/insns/truncu_w_d.h b/riscv/insns/truncu_w_d.h index bb674f6..4187e53 100644 --- a/riscv/insns/truncu_w_d.h +++ b/riscv/insns/truncu_w_d.h @@ -1,3 +1,3 @@ require_fp; -FRDR = f64_to_ui32_r_minMag(FRS1,true); +RDR = f64_to_ui32_r_minMag(FRS1,true); set_fp_exceptions; diff --git a/riscv/insns/truncu_w_s.h b/riscv/insns/truncu_w_s.h index d85f9e5..2014c2b 100644 --- a/riscv/insns/truncu_w_s.h +++ b/riscv/insns/truncu_w_s.h @@ -1,3 +1,3 @@ require_fp; -FRDR = f32_to_ui32_r_minMag(FRS1,true); +RDR = f32_to_ui32_r_minMag(FRS1,true); set_fp_exceptions; |