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author | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2010-12-27 15:34:05 -0800 |
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committer | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2010-12-27 15:34:05 -0800 |
commit | 0ea058a5a81930e038dfd3a6a318f4d32893ac5a (patch) | |
tree | 57e36f7cc02474cfd455f75592c531de1579eead /riscv | |
parent | 53e36319bc38b17d1cc98037322391f0606e8239 (diff) | |
download | spike-0ea058a5a81930e038dfd3a6a318f4d32893ac5a.zip spike-0ea058a5a81930e038dfd3a6a318f4d32893ac5a.tar.gz spike-0ea058a5a81930e038dfd3a6a318f4d32893ac5a.tar.bz2 |
[sim] fixed some compiler warnings
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/insns/div.h | 2 | ||||
-rw-r--r-- | riscv/insns/divw.h | 2 | ||||
-rw-r--r-- | riscv/insns/rem.h | 2 | ||||
-rw-r--r-- | riscv/insns/remw.h | 2 | ||||
-rw-r--r-- | riscv/sim.cc | 1 |
5 files changed, 5 insertions, 4 deletions
diff --git a/riscv/insns/div.h b/riscv/insns/div.h index f6a9b6b..1f61cf1 100644 --- a/riscv/insns/div.h +++ b/riscv/insns/div.h @@ -1,5 +1,5 @@ require64; -if(RS2 == 0 || sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1) +if(RS2 == 0 || (sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1)) RD = sreg_t(RS1) < 0 ? INT64_MIN : INT64_MAX; else RD = sreg_t(RS1) / sreg_t(RS2); diff --git a/riscv/insns/divw.h b/riscv/insns/divw.h index 0537469..bfc982a 100644 --- a/riscv/insns/divw.h +++ b/riscv/insns/divw.h @@ -1,4 +1,4 @@ -if(int32_t(RS2) == 0 || int32_t(RS1) == INT32_MIN && int32_t(RS2) == -1) +if(int32_t(RS2) == 0 || (int32_t(RS1) == INT32_MIN && int32_t(RS2) == -1)) RD = sext32(int32_t(RS1) < 0 ? INT32_MIN : INT32_MAX); else RD = sext32(int32_t(RS1)/int32_t(RS2)); diff --git a/riscv/insns/rem.h b/riscv/insns/rem.h index 146dbc6..1bc94f2 100644 --- a/riscv/insns/rem.h +++ b/riscv/insns/rem.h @@ -1,5 +1,5 @@ require64; -if(RS2 == 0 || sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1) +if(RS2 == 0 || (sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1)) RD = 0; else RD = sreg_t(RS1) % sreg_t(RS2); diff --git a/riscv/insns/remw.h b/riscv/insns/remw.h index 0e68dc6..eb23ef1 100644 --- a/riscv/insns/remw.h +++ b/riscv/insns/remw.h @@ -1,4 +1,4 @@ -if(int32_t(RS2) == 0 || int32_t(RS1) == INT32_MIN && int32_t(RS2) == -1) +if(int32_t(RS2) == 0 || (int32_t(RS1) == INT32_MIN && int32_t(RS2) == -1)) RD = 0; else RD = sext32(int32_t(RS1) % int32_t(RS2)); diff --git a/riscv/sim.cc b/riscv/sim.cc index 8b04aa2..ffcb186 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -4,6 +4,7 @@ #include <sys/mman.h> #include <map> #include <iostream> +#include <climits> sim_t::sim_t(int _nprocs, size_t _memsz, appserver_link_t* _applink) : applink(_applink), |