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authorAndrew Waterman <waterman@s141.Millennium.Berkeley.EDU>2010-07-18 18:28:05 -0700
committerAndrew Waterman <waterman@s141.Millennium.Berkeley.EDU>2010-07-18 18:28:05 -0700
commit01c01cc36f006cfb03cd6d1c5a68f926b93f7787 (patch)
tree1bc5333057ff935073a595834092e4dd0936e34d /riscv/processor.h
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Reorganized directory structure
Moved cross-compiler to /xcc/ rather than / Added ISA sim in /sim/ Added Proxy Kernel in /pk/ (to be cleaned up) Added opcode map to /opcodes/ (ditto) Added documentation to /doc/
Diffstat (limited to 'riscv/processor.h')
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diff --git a/riscv/processor.h b/riscv/processor.h
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+#ifndef _RISCV_PROCESSOR_H
+#define _RISCV_PROCESSOR_H
+
+#include <cstring>
+#include "decode.h"
+#include "trap.h"
+#include "mmu.h"
+
+class processor_t
+{
+public:
+ processor_t(int _id, char* _mem, size_t _memsz);
+ void step(size_t n, bool noisy);
+
+private:
+ // architected state
+ reg_t R[NGPR];
+ reg_t pc;
+ reg_t epc;
+ reg_t badvaddr;
+ reg_t ebase;
+ uint32_t id;
+ uint32_t sr;
+ int gprlen;
+
+ // shared memory
+ mmu_t mmu;
+
+ // counters
+ reg_t counters[32];
+
+ // functions
+ void set_sr(uint32_t val);
+ void take_trap(trap_t t);
+ void disasm(insn_t insn, reg_t pc);
+
+ friend class sim_t;
+};
+
+#endif