diff options
author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-08-10 22:55:07 +0800 |
---|---|---|
committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-08-10 23:05:58 +0800 |
commit | ce34edb0eecec520d6d2cfec5bda57ca90a69f14 (patch) | |
tree | f5f5da62f53bced28e38349a1b41983bb916dcfa /riscv/debug_module.cc | |
parent | 2aaa89c0cf8fe0f45d284c0847f11d175eb82e03 (diff) | |
download | spike-ce34edb0eecec520d6d2cfec5bda57ca90a69f14.zip spike-ce34edb0eecec520d6d2cfec5bda57ca90a69f14.tar.gz spike-ce34edb0eecec520d6d2cfec5bda57ca90a69f14.tar.bz2 |
Add space between if/while/switch and '('
Add space between ')' and '{'
Diffstat (limited to 'riscv/debug_module.cc')
-rw-r--r-- | riscv/debug_module.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index 16520d1..d297f14 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -215,7 +215,7 @@ bool debug_module_t::store(reg_t addr, size_t len, const uint8_t* bytes) } } if (dmcontrol.hartsel == id) { - if (0 == (debug_rom_flags[id] & (1 << DEBUG_ROM_FLAG_GO))){ + if (0 == (debug_rom_flags[id] & (1 << DEBUG_ROM_FLAG_GO))) { if (dmcontrol.hartsel == id) { abstract_command_completed = true; } |