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author | Tim Newsome <tim@sifive.com> | 2018-08-23 20:36:41 -0700 |
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committer | Andrew Waterman <aswaterman@gmail.com> | 2018-08-23 20:36:41 -0700 |
commit | 176ff23c6fa3dde20a027ce3f4fea13b3342c223 (patch) | |
tree | 28c993d5ccff27c44c4f015f2573c4f18a953379 /riscv/debug_module.cc | |
parent | fad88d81408746069ca138f498282ef5881179e8 (diff) | |
download | spike-176ff23c6fa3dde20a027ce3f4fea13b3342c223.zip spike-176ff23c6fa3dde20a027ce3f4fea13b3342c223.tar.gz spike-176ff23c6fa3dde20a027ce3f4fea13b3342c223.tar.bz2 |
Add dummy custom debug registers, to test OpenOCD. (#233)
Diffstat (limited to 'riscv/debug_module.cc')
-rw-r--r-- | riscv/debug_module.cc | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index f271d74..b209347 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -25,6 +25,7 @@ debug_module_t::debug_module_t(sim_t *sim, unsigned progbufsize, unsigned max_bu require_authentication(require_authentication), debug_progbuf_start(debug_data_start - program_buffer_bytes), debug_abstract_start(debug_progbuf_start - debug_abstract_size*4), + custom_base(0), sim(sim) { D(fprintf(stderr, "debug_data_start=0x%x\n", debug_data_start)); @@ -599,6 +600,20 @@ bool debug_module_t::perform_abstract_command() } } + } else if (regno >= 0xc000 && (regno & 1) == 1) { + // Support odd-numbered custom registers, to allow for debugger testing. + unsigned custom_number = regno - 0xc000; + abstractcs.cmderr = CMDERR_NONE; + if (write) { + // Writing V to custom register N will cause future reads of N to + // return V, reads of N-1 will return V-1, etc. + custom_base = read32(dmdata, 0) - custom_number; + } else { + write32(dmdata, 0, custom_number + custom_base); + write32(dmdata, 1, 0); + } + return true; + } else { abstractcs.cmderr = CMDERR_NOTSUP; return true; |