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authorChih-Min Chao <chihmin.chao@sifive.com>2019-06-07 09:57:52 -0700
committerChih-Min Chao <chihmin.chao@sifive.com>2019-06-07 09:57:52 -0700
commita9657f307df6f56eb0898962ccc5a9da4d5c3d29 (patch)
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parent17bfc2e5df578baa1758403ffd35a701de3267bd (diff)
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rvv: add vector support to readme
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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@@ -18,6 +18,7 @@ Spike supports the following RISC-V ISA features:
- D extension, v2.2
- Q extension, v2.2
- C extension, v2.0
+ - V extension, v0.7.1
- Conformance to both RVWMO and RVTSO (Spike is sequentially consistent)
- Machine, Supervisor, and User modes, v1.11
- Debug v0.14