scalar-crypto: Encoding fixes for v0.9.2

- Reverts the AES32 and SM4 instruction encodings back to a normal R-type
  encoding, per the advice of the architecture reviewers.

 On branch scalar-crypto-v0.9.2
 Changes to be committed:
	modified:   riscv/encoding.h
	modified:   riscv/insns/aes32dsi.h
	modified:   riscv/insns/aes32dsmi.h
	modified:   riscv/insns/aes32esi.h
	modified:   riscv/insns/aes32esmi.h
	modified:   riscv/insns/sm4ed.h
	modified:   riscv/insns/sm4ks.h

7 files changed, 12 insertions, 22 deletions

diff --git a/riscv/encoding.h b/riscv/encoding.h
index 7c02e14..ebd401c 100644
--- a/riscv/encoding.h
+++ b/riscv/encoding.h
@@ -927,9 +927,9 @@
 #define MATCH_POLLENTROPY 0xf1500073
 #define MASK_GETNOISE  0xfffff07f
 #define MATCH_GETNOISE 0x7a900073
-#define MASK_SM4ED  0x3e007fff
+#define MASK_SM4ED  0x3e00707f
 #define MATCH_SM4ED 0x30000033
-#define MASK_SM4KS  0x3e007fff
+#define MASK_SM4KS  0x3e00707f
 #define MATCH_SM4KS 0x34000033
 #define MASK_SM3P0  0xfff0707f
 #define MATCH_SM3P0 0x10801013
@@ -961,13 +961,13 @@
 #define MATCH_AES64IM 0x30001013
 #define MASK_AES64KS2  0xfe00707f
 #define MATCH_AES64KS2 0x7e000033
-#define MASK_AES32ESMI  0x3e007fff
+#define MASK_AES32ESMI  0x3e00707f
 #define MATCH_AES32ESMI 0x36000033
-#define MASK_AES32ESI  0x3e007fff
+#define MASK_AES32ESI  0x3e00707f
 #define MATCH_AES32ESI 0x32000033
-#define MASK_AES32DSMI  0x3e007fff
+#define MASK_AES32DSMI  0x3e00707f
 #define MATCH_AES32DSMI 0x3e000033
-#define MASK_AES32DSI  0x3e007fff
+#define MASK_AES32DSI  0x3e00707f
 #define MATCH_AES32DSI 0x3a000033
 #define MASK_AES64KS1I  0xff00707f
 #define MATCH_AES64KS1I 0x31001013
diff --git a/riscv/insns/aes32dsi.h b/riscv/insns/aes32dsi.h
index 07d0363..81534f0 100644
--- a/riscv/insns/aes32dsi.h
+++ b/riscv/insns/aes32dsi.h
@@ -3,7 +3,6 @@
 
 require_rv32;
 require_extension('K');
-require(RD == 0); // Additional decoding required for RV32
 
 uint8_t     bs = insn.bs();
 
@@ -13,6 +12,5 @@ uint32_t     u = x;
 
 u = (u << (8*bs)) | (u >> (32-8*bs));
 
-uint64_t    rd = insn.rs1(); // RD sourced from RS1 field.
-WRITE_REG(rd, u ^ RS1);
+WRITE_RD(u ^ RS1);
 
diff --git a/riscv/insns/aes32dsmi.h b/riscv/insns/aes32dsmi.h
index 6d157ac..417b128 100644
--- a/riscv/insns/aes32dsmi.h
+++ b/riscv/insns/aes32dsmi.h
@@ -3,7 +3,6 @@
 
 require_rv32;
 require_extension('K');
-require(RD == 0); // Additional decoding required for RV32
 
 uint8_t     bs = insn.bs();
 
@@ -18,6 +17,5 @@ u = (AES_GFMUL(x,0xb) << 24) |
 
 u = (u << (8*bs)) | (u >> (32-8*bs));
 
-uint64_t    rd = insn.rs1(); // RD sourced from RS1 field.
-WRITE_REG(rd, u ^ RS1);
+WRITE_RD(u ^ RS1);
 
diff --git a/riscv/insns/aes32esi.h b/riscv/insns/aes32esi.h
index e24124d..afa38c9 100644
--- a/riscv/insns/aes32esi.h
+++ b/riscv/insns/aes32esi.h
@@ -3,7 +3,6 @@
 
 require_rv32;
 require_extension('K');
-require(RD == 0); // Additional decoding required for RV32
 
 uint8_t     bs = insn.bs();
 
@@ -13,6 +12,5 @@ uint32_t     u = x;
 
 u = (u << (8*bs)) | (u >> (32-8*bs));
 
-uint64_t    rd = insn.rs1(); // RD sourced from RS1 field.
-WRITE_REG(rd, u ^ RS1);
+WRITE_RD(u ^ RS1);
 
diff --git a/riscv/insns/aes32esmi.h b/riscv/insns/aes32esmi.h
index 9768201..411195e 100644
--- a/riscv/insns/aes32esmi.h
+++ b/riscv/insns/aes32esmi.h
@@ -3,7 +3,6 @@
 
 require_rv32;
 require_extension('K');
-require(RD == 0); // Additional decoding required for RV32
 
 uint8_t     bs = insn.bs();
 
@@ -18,6 +17,5 @@ u = (AES_GFMUL(x,3) << 24) |
 
 u = (u << (8*bs)) | (u >> (32-8*bs));
 
-uint64_t    rd = insn.rs1(); // RD sourced from RS1 field.
-WRITE_REG(rd, u ^ RS1);
+WRITE_RD(u ^ RS1);
 
diff --git a/riscv/insns/sm4ed.h b/riscv/insns/sm4ed.h
index 5583335..738bc69 100644
--- a/riscv/insns/sm4ed.h
+++ b/riscv/insns/sm4ed.h
@@ -17,7 +17,6 @@ uint32_t linear = sb_out ^  (sb_out         <<  8) ^
 uint32_t rotl   = (linear << (8*bs)) | (linear >> (32-8*bs));
 
 uint32_t result = rotl ^ RS1;
-uint64_t rd     = insn.rs1(); // RD sourced from RS1 field.
 
-WRITE_REG(rd, zext_xlen(result));
+WRITE_RD(zext_xlen(result));
 
diff --git a/riscv/insns/sm4ks.h b/riscv/insns/sm4ks.h
index 589eb97..5758d57 100644
--- a/riscv/insns/sm4ks.h
+++ b/riscv/insns/sm4ks.h
@@ -15,7 +15,6 @@ uint32_t x      = sb_out ^
 uint32_t rotl   = (x << (8*bs)) | (x >> (32-8*bs));
 
 uint32_t result = rotl ^ RS1;
-uint64_t rd     = insn.rs1(); // RD sourced from RS1 field.
 
-WRITE_REG(rd, zext_xlen(result));
+WRITE_RD(zext_xlen(result));