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author | Andrew Waterman <andrew@sifive.com> | 2021-07-28 15:01:14 -0700 |
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committer | GitHub <noreply@github.com> | 2021-07-28 15:01:14 -0700 |
commit | b0a2222b2ad9dc4f2bca0f54c68a9b00b8d89b1e (patch) | |
tree | 470112e8f3fdd2630f044716c647154574ec7c90 | |
parent | a13051f5406ee0cfd88d5d26cba8fe2587370a92 (diff) | |
parent | 8e023fa06a47cca7c7da50b5358ed9dc48f579f9 (diff) | |
download | spike-b0a2222b2ad9dc4f2bca0f54c68a9b00b8d89b1e.zip spike-b0a2222b2ad9dc4f2bca0f54c68a9b00b8d89b1e.tar.gz spike-b0a2222b2ad9dc4f2bca0f54c68a9b00b8d89b1e.tar.bz2 |
Merge pull request #759 from ben-marshall/scalar-crypto
Scalar crypto: post arch review updates
-rw-r--r-- | disasm/disasm.cc | 8 | ||||
-rw-r--r-- | riscv/encoding.h | 29 | ||||
-rw-r--r-- | riscv/insns/sm3p0.h | 2 | ||||
-rw-r--r-- | riscv/insns/sm3p1.h | 2 | ||||
-rw-r--r-- | riscv/insns/sm4ed.h | 2 | ||||
-rw-r--r-- | riscv/insns/sm4ks.h | 2 | ||||
-rw-r--r-- | riscv/processor.cc | 12 |
7 files changed, 11 insertions, 46 deletions
diff --git a/disasm/disasm.cc b/disasm/disasm.cc index fe1e24e..b6ad437 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -447,11 +447,7 @@ disassembler_t::disassembler_t(int xlen) #define DECLARE_INSN(code, match, mask) \ const uint32_t match_##code = match; \ const uint32_t mask_##code = mask; - #define DECLARE_RV32_ONLY(code) {} - #define DECLARE_RV64_ONLY(code) {} #include "encoding.h" - #undef DECLARE_RV64_INSN - #undef DECLARE_RV32_INSN #undef DECLARE_INSN // explicit per-instruction disassembly @@ -1682,11 +1678,7 @@ disassembler_t::disassembler_t(int xlen) // provide a default disassembly for all instructions as a fallback #define DECLARE_INSN(code, match, mask) \ add_insn(new disasm_insn_t(#code " (args unknown)", match, mask, {})); - #define DECLARE_RV32_ONLY(code) {} - #define DECLARE_RV64_ONLY(code) {} #include "encoding.h" - #undef DECLARE_RV64_INSN - #undef DECLARE_RV32_INSN #undef DECLARE_INSN } diff --git a/riscv/encoding.h b/riscv/encoding.h index 39e9aa0..8ad3a6c 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -965,13 +965,13 @@ #define MASK_AES64KS2 0xfe00707f #define MATCH_AES64KS2 0x7e000033 #define MASK_AES32ESMI 0x3e00707f -#define MATCH_AES32ESMI 0x36000033 +#define MATCH_AES32ESMI 0x26000033 #define MASK_AES32ESI 0x3e00707f -#define MATCH_AES32ESI 0x32000033 +#define MATCH_AES32ESI 0x22000033 #define MASK_AES32DSMI 0x3e00707f -#define MATCH_AES32DSMI 0x3e000033 +#define MATCH_AES32DSMI 0x2e000033 #define MASK_AES32DSI 0x3e00707f -#define MATCH_AES32DSI 0x3a000033 +#define MATCH_AES32DSI 0x2a000033 #define MASK_AES64KS1I 0xff00707f #define MATCH_AES64KS1I 0x31001013 #define MASK_AES64IM 0xfff0707f @@ -3419,21 +3419,10 @@ DECLARE_INSN(aes64es, MATCH_AES64ES, MASK_AES64ES) DECLARE_INSN(aes64esm, MATCH_AES64ESM, MASK_AES64ESM) DECLARE_INSN(aes64ds, MATCH_AES64DS, MASK_AES64DS) DECLARE_INSN(aes64dsm, MATCH_AES64DSM, MASK_AES64DSM) -DECLARE_RV64_ONLY(aes64ks1i) -DECLARE_RV64_ONLY(aes64ks2) -DECLARE_RV64_ONLY(aes64im) -DECLARE_RV64_ONLY(aes64es) -DECLARE_RV64_ONLY(aes64esm) -DECLARE_RV64_ONLY(aes64ds) -DECLARE_RV64_ONLY(aes64dsm) DECLARE_INSN(aes32esi, MATCH_AES32ESI, MASK_AES32ESI) DECLARE_INSN(aes32esmi, MATCH_AES32ESMI, MASK_AES32ESMI) DECLARE_INSN(aes32dsi, MATCH_AES32DSI, MASK_AES32DSI) DECLARE_INSN(aes32dsmi, MATCH_AES32DSMI, MASK_AES32DSMI) -DECLARE_RV32_ONLY(aes32esi) -DECLARE_RV32_ONLY(aes32esmi) -DECLARE_RV32_ONLY(aes32dsi) -DECLARE_RV32_ONLY(aes32dsmi) DECLARE_INSN(sha256sig0, MATCH_SHA256SIG0, MASK_SHA256SIG0) DECLARE_INSN(sha256sig1, MATCH_SHA256SIG1, MASK_SHA256SIG1) DECLARE_INSN(sha256sum0, MATCH_SHA256SUM0, MASK_SHA256SUM0) @@ -3446,20 +3435,10 @@ DECLARE_INSN(sha512sig1l, MATCH_SHA512SIG1L, MASK_SHA512SIG1L) DECLARE_INSN(sha512sig1h, MATCH_SHA512SIG1H, MASK_SHA512SIG1H) DECLARE_INSN(sha512sum0r, MATCH_SHA512SUM0R, MASK_SHA512SUM0R) DECLARE_INSN(sha512sum1r, MATCH_SHA512SUM1R, MASK_SHA512SUM1R) -DECLARE_RV32_ONLY(sha512sig0l) -DECLARE_RV32_ONLY(sha512sig0h) -DECLARE_RV32_ONLY(sha512sig1l) -DECLARE_RV32_ONLY(sha512sig1h) -DECLARE_RV32_ONLY(sha512sum0r) -DECLARE_RV32_ONLY(sha512sum1r) DECLARE_INSN(sha512sig0, MATCH_SHA512SIG0, MASK_SHA512SIG0) DECLARE_INSN(sha512sig1, MATCH_SHA512SIG1, MASK_SHA512SIG1) DECLARE_INSN(sha512sum0, MATCH_SHA512SUM0, MASK_SHA512SUM0) DECLARE_INSN(sha512sum1, MATCH_SHA512SUM1, MASK_SHA512SUM1) -DECLARE_RV64_ONLY(sha512sig0) -DECLARE_RV64_ONLY(sha512sig1) -DECLARE_RV64_ONLY(sha512sum0) -DECLARE_RV64_ONLY(sha512sum1) DECLARE_INSN(pollentropy, MATCH_POLLENTROPY, MASK_POLLENTROPY) DECLARE_INSN(getnoise, MATCH_GETNOISE, MASK_GETNOISE) DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) diff --git a/riscv/insns/sm3p0.h b/riscv/insns/sm3p0.h index 1ff3945..5b692b2 100644 --- a/riscv/insns/sm3p0.h +++ b/riscv/insns/sm3p0.h @@ -7,7 +7,7 @@ uint32_t src = RS1; uint32_t result = src ^ ROL32(src, 9) ^ ROL32(src, 17); WRITE_RD( - zext_xlen(result) + sext_xlen(result) ); #undef ROL32 diff --git a/riscv/insns/sm3p1.h b/riscv/insns/sm3p1.h index 8fc1161..9570171 100644 --- a/riscv/insns/sm3p1.h +++ b/riscv/insns/sm3p1.h @@ -7,7 +7,7 @@ uint32_t src = RS1; uint32_t result = src ^ ROL32(src, 15) ^ ROL32(src, 23); WRITE_RD( - zext_xlen(result) + sext_xlen(result) ); #undef ROL32 diff --git a/riscv/insns/sm4ed.h b/riscv/insns/sm4ed.h index 738bc69..07f953b 100644 --- a/riscv/insns/sm4ed.h +++ b/riscv/insns/sm4ed.h @@ -18,5 +18,5 @@ uint32_t rotl = (linear << (8*bs)) | (linear >> (32-8*bs)); uint32_t result = rotl ^ RS1; -WRITE_RD(zext_xlen(result)); +WRITE_RD(sext_xlen(result)); diff --git a/riscv/insns/sm4ks.h b/riscv/insns/sm4ks.h index 5758d57..9f39c64 100644 --- a/riscv/insns/sm4ks.h +++ b/riscv/insns/sm4ks.h @@ -16,5 +16,5 @@ uint32_t rotl = (x << (8*bs)) | (x >> (32-8*bs)); uint32_t result = rotl ^ RS1; -WRITE_RD(zext_xlen(result)); +WRITE_RD(sext_xlen(result)); diff --git a/riscv/processor.cc b/riscv/processor.cc index fa574ff..655dd18 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -1860,14 +1860,8 @@ void processor_t::register_extension(extension_t* x) void processor_t::register_base_instructions() { #define DECLARE_INSN(name, match, mask) \ - insn_bits_t name##_match = (match), name##_mask = (mask); \ - unsigned name##_arch_en = (unsigned)-1; - #define DECLARE_RV32_ONLY(name) {name##_arch_en = 32;} - #define DECLARE_RV64_ONLY(name) {name##_arch_en = 64;} - + insn_bits_t name##_match = (match), name##_mask = (mask); #include "encoding.h" - #undef DECLARE_RV64_INSN - #undef DECLARE_RV32_INSN #undef DECLARE_INSN #define DEFINE_INSN(name) \ @@ -1876,8 +1870,8 @@ void processor_t::register_base_instructions() register_insn((insn_desc_t){ \ name##_match, \ name##_mask, \ - (name##_arch_en & 32) ? rv32_##name : nullptr, \ - (name##_arch_en & 64) ? rv64_##name : nullptr}); + rv32_##name, \ + rv64_##name}); #include "insn_list.h" #undef DEFINE_INSN |