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| author | Dan Lustig <dlustig@nvidia.com> | 2021-07-22 07:36:18 -0400 |
|---|---|---|
| committer | Dan Lustig <dlustig@nvidia.com> | 2021-07-22 07:36:18 -0400 |
| commit | 80be4e21c3af7fe2966788ce538d3e3c3b0d60e3 (patch) | |
| tree | 45a0cdfc4bcb03ea8f53d1e3c45ddce366ffe0b1 | |
| parent | cb8f09a4d6fed30527fdd832b885c898b4591a5f (diff) | |
| download | spike-80be4e21c3af7fe2966788ce538d3e3c3b0d60e3.zip spike-80be4e21c3af7fe2966788ce538d3e3c3b0d60e3.tar.gz spike-80be4e21c3af7fe2966788ce538d3e3c3b0d60e3.tar.bz2 | |
Non-leaf PTEs with D/A/U==1 are reserved
...and hence should trigger page faults
Thanks to @pdonahue-ventana for pointing this out:
https://github.com/riscv/riscv-tests/issues/352
| -rw-r--r-- | riscv/mmu.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index bc2dcc8..fe96870 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -415,6 +415,8 @@ reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode, bool virt, bool mxr) if (pte & PTE_RSVD) { break; } else if (PTE_TABLE(pte)) { // next level of page table + if (pte & (PTE_D | PTE_A | PTE_U)) + break; base = ppn << PGSHIFT; } else if ((pte & PTE_U) ? s_mode && (type == FETCH || !sum) : !s_mode) { break; |