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author | rbuchner <ryan.buchner@arilinc.com> | 2023-05-01 09:13:47 -0700 |
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committer | rbuchner <ryan.buchner@arilinc.com> | 2023-05-11 23:00:59 -0700 |
commit | a30a0d63677151cc688fa4e0a05ac664e63d94f4 (patch) | |
tree | 8bb0486dcafa78d700c92afcf870541a686d1aba | |
parent | 33fbc2df39df914d3462bede4112db7966d49a3c (diff) | |
download | spike-a30a0d63677151cc688fa4e0a05ac664e63d94f4.zip spike-a30a0d63677151cc688fa4e0a05ac664e63d94f4.tar.gz spike-a30a0d63677151cc688fa4e0a05ac664e63d94f4.tar.bz2 |
Use passed in virtual bit for creating traps in take_trigger_action() rahter than state.v
Fixes case 1 from https://github.com/riscv-software-src/riscv-isa-sim/issues/872
-rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 0ccb651..74a0b8f 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -899,7 +899,7 @@ void processor_t::take_trigger_action(triggers::action_t action, reg_t breakpoin enter_debug_mode(DCSR_CAUSE_HWBP); break; case triggers::ACTION_DEBUG_EXCEPTION: { - trap_breakpoint trap(state.v, breakpoint_tval); + trap_breakpoint trap(virt, breakpoint_tval); take_trap(trap, epc); break; } |