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| author | Aaron Durbin <adurbin@rivosinc.com> | 2023-01-27 08:34:06 -0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@rivosinc.com> | 2023-01-27 09:31:27 -0800 |
| commit | 53222130f60b2d651970a23a60b4f3ab86731ba5 (patch) | |
| tree | 35d519483e5463d7b43b28e5b31645e5120f0f70 | |
| parent | dc280587d646f01c3dbbfd62f01023a05f84ef3c (diff) | |
| download | spike-53222130f60b2d651970a23a60b4f3ab86731ba5.zip spike-53222130f60b2d651970a23a60b4f3ab86731ba5.tar.gz spike-53222130f60b2d651970a23a60b4f3ab86731ba5.tar.bz2 | |
Add Svadu CSR bit definitions
The Svadu extension adds a HADE field (bit 61) to both
menvcfg and henvcfg. Add the definitions so they can be utilized.
| -rw-r--r-- | riscv/encoding.h | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/riscv/encoding.h b/riscv/encoding.h index f899a64..725630e 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -/* Copyright (c) 2022 RISC-V International */ +/* Copyright (c) 2023 RISC-V International */ /* * This file is auto-generated by running 'make' in - * https://github.com/riscv/riscv-opcodes (4d7f46e) + * https://github.com/riscv/riscv-opcodes (ebd4dbf) */ #ifndef RISCV_CSR_ENCODING_H @@ -156,9 +156,11 @@ #define MENVCFG_CBIE 0x00000030 #define MENVCFG_CBCFE 0x00000040 #define MENVCFG_CBZE 0x00000080 +#define MENVCFG_HADE 0x2000000000000000 #define MENVCFG_PBMTE 0x4000000000000000 #define MENVCFG_STCE 0x8000000000000000 +#define MENVCFGH_HADE 0x20000000 #define MENVCFGH_PBMTE 0x40000000 #define MENVCFGH_STCE 0x80000000 @@ -191,9 +193,11 @@ #define HENVCFG_CBIE 0x00000030 #define HENVCFG_CBCFE 0x00000040 #define HENVCFG_CBZE 0x00000080 +#define HENVCFG_HADE 0x2000000000000000 #define HENVCFG_PBMTE 0x4000000000000000 #define HENVCFG_STCE 0x8000000000000000 +#define HENVCFGH_HADE 0x20000000 #define HENVCFGH_PBMTE 0x40000000 #define HENVCFGH_STCE 0x80000000 |