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| author | Andrew Waterman <andrew@sifive.com> | 2023-11-15 16:11:45 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-11-15 16:12:52 -0800 |
| commit | 874ac597c5002389303eb49a92ac13f08558639a (patch) | |
| tree | e0f26550919dbcf064c9c34b36c6b20ba4374862 | |
| parent | be5dee0bafb413c9ac8845ca144db9b7641941b2 (diff) | |
| download | spike-874ac597c5002389303eb49a92ac13f08558639a.zip spike-874ac597c5002389303eb49a92ac13f08558639a.tar.gz spike-874ac597c5002389303eb49a92ac13f08558639a.tar.bz2 | |
Don't enforce alignment constraints vwsll.v[xi] rs1 arg
rs1 doesn't represent a vector arg in this case, so the instructions
were broken for (rs1 % ceil(LMUL)) != 0.
Resolves #1505
| -rw-r--r-- | riscv/zvk_ext_macros.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/zvk_ext_macros.h b/riscv/zvk_ext_macros.h index 75aa56a..f094629 100644 --- a/riscv/zvk_ext_macros.h +++ b/riscv/zvk_ext_macros.h @@ -750,7 +750,7 @@ // - 'rs1', unsigned, SEW width, by value, constant. #define VI_ZVK_VX_WIDENING_ULOOP(BODY) \ do { \ - VI_CHECK_DSS(true); \ + VI_CHECK_DSS(false); \ VI_LOOP_BASE \ switch (sew) { \ case e8: { \ @@ -788,7 +788,7 @@ // - 'zimm5', unsigned, SEW width, by value, constant. #define VI_ZVK_VI_WIDENING_ULOOP(BODY) \ do { \ - VI_CHECK_DSS(true); \ + VI_CHECK_DSS(false); \ VI_LOOP_BASE \ switch (sew) { \ case e8: { \ |