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| author | Andrew Waterman <andrew@sifive.com> | 2018-01-03 13:06:21 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-01-03 13:06:21 -0800 |
| commit | 874e55888f23024899db93231d2b7c672fab33bb (patch) | |
| tree | a981f3a1a01d1795f8f1d4f70c5d81b7d5160b54 | |
| parent | 0185d369153b099be0c363a4ad6a52cec19b80bd (diff) | |
| download | spike-874e55888f23024899db93231d2b7c672fab33bb.zip spike-874e55888f23024899db93231d2b7c672fab33bb.tar.gz spike-874e55888f23024899db93231d2b7c672fab33bb.tar.bz2 | |
Add some missing RVC instructions to disassembler
| -rw-r--r-- | spike_main/disasm.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/spike_main/disasm.cc b/spike_main/disasm.cc index 49f4de2..982064d 100644 --- a/spike_main/disasm.cc +++ b/spike_main/disasm.cc @@ -545,6 +545,9 @@ disassembler_t::disassembler_t(int xlen) DISASM_INSN("lui", c_lui, 0, {&xrd, &rvc_uimm}); DISASM_INSN("addi", c_addi, 0, {&xrd, &xrd, &rvc_imm}); DISASM_INSN("slli", c_slli, 0, {&xrd, &rvc_shamt}); + DISASM_INSN("srli", c_srli, 0, {&rvc_rs1s, &rvc_rs1s, &rvc_shamt}); + DISASM_INSN("srai", c_srai, 0, {&rvc_rs1s, &rvc_rs1s, &rvc_shamt}); + DISASM_INSN("andi", c_andi, 0, {&rvc_rs1s, &rvc_rs1s, &rvc_imm}); DISASM_INSN("mv", c_mv, 0, {&xrd, &rvc_rs2}); DISASM_INSN("add", c_add, 0, {&xrd, &xrd, &rvc_rs2}); DISASM_INSN("addw", c_addw, 0, {&rvc_rs1s, &rvc_rs1s, &rvc_rs2s}); |