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author | Tim Newsome <tim@sifive.com> | 2018-01-09 12:29:34 -0800 |
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committer | Tim Newsome <tim@sifive.com> | 2018-01-09 12:29:34 -0800 |
commit | 11780eabc0147a58c575d089c4afe5732b55bb05 (patch) | |
tree | 18323d943811c0843334d38f859fcf41d39786f7 | |
parent | fd0dbf46c3d9f8b005d35dfed79dbd4b4b0f974a (diff) | |
download | spike-11780eabc0147a58c575d089c4afe5732b55bb05.zip spike-11780eabc0147a58c575d089c4afe5732b55bb05.tar.gz spike-11780eabc0147a58c575d089c4afe5732b55bb05.tar.bz2 |
Use new debug_defines.h.
-rw-r--r-- | riscv/debug_defines.h | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/riscv/debug_defines.h b/riscv/debug_defines.h index 1d3e1c0..58826f0 100644 --- a/riscv/debug_defines.h +++ b/riscv/debug_defines.h @@ -295,7 +295,7 @@ * * Other values are reserved for future use. */ -#define CSR_TDATA1_TYPE_OFFSET XLEN-4 +#define CSR_TDATA1_TYPE_OFFSET (XLEN-4) #define CSR_TDATA1_TYPE_LENGTH 4 #define CSR_TDATA1_TYPE (0xfULL << CSR_TDATA1_TYPE_OFFSET) /* @@ -307,14 +307,14 @@ * * This bit is only writable from Debug Mode. */ -#define CSR_TDATA1_DMODE_OFFSET XLEN-5 +#define CSR_TDATA1_DMODE_OFFSET (XLEN-5) #define CSR_TDATA1_DMODE_LENGTH 1 #define CSR_TDATA1_DMODE (0x1ULL << CSR_TDATA1_DMODE_OFFSET) /* * Trigger-specific data. */ #define CSR_TDATA1_DATA_OFFSET 0 -#define CSR_TDATA1_DATA_LENGTH XLEN - 5 +#define CSR_TDATA1_DATA_LENGTH (XLEN - 5) #define CSR_TDATA1_DATA (((1L<<XLEN - 5)-1) << CSR_TDATA1_DATA_OFFSET) #define CSR_TDATA2 0x7a2 #define CSR_TDATA2_DATA_OFFSET 0 @@ -325,10 +325,10 @@ #define CSR_TDATA3_DATA_LENGTH XLEN #define CSR_TDATA3_DATA (((1L<<XLEN)-1) << CSR_TDATA3_DATA_OFFSET) #define CSR_MCONTROL 0x7a1 -#define CSR_MCONTROL_TYPE_OFFSET XLEN-4 +#define CSR_MCONTROL_TYPE_OFFSET (XLEN-4) #define CSR_MCONTROL_TYPE_LENGTH 4 #define CSR_MCONTROL_TYPE (0xfULL << CSR_MCONTROL_TYPE_OFFSET) -#define CSR_MCONTROL_DMODE_OFFSET XLEN-5 +#define CSR_MCONTROL_DMODE_OFFSET (XLEN-5) #define CSR_MCONTROL_DMODE_LENGTH 1 #define CSR_MCONTROL_DMODE (0x1ULL << CSR_MCONTROL_DMODE_OFFSET) /* @@ -339,7 +339,7 @@ * corresponds to the maximum NAPOT range, which is $2^{63}$ bytes in * size. */ -#define CSR_MCONTROL_MASKMAX_OFFSET XLEN-11 +#define CSR_MCONTROL_MASKMAX_OFFSET (XLEN-11) #define CSR_MCONTROL_MASKMAX_LENGTH 6 #define CSR_MCONTROL_MASKMAX (0x3fULL << CSR_MCONTROL_MASKMAX_OFFSET) /* @@ -478,10 +478,10 @@ #define CSR_MCONTROL_LOAD_LENGTH 1 #define CSR_MCONTROL_LOAD (0x1ULL << CSR_MCONTROL_LOAD_OFFSET) #define CSR_ICOUNT 0x7a1 -#define CSR_ICOUNT_TYPE_OFFSET XLEN-4 +#define CSR_ICOUNT_TYPE_OFFSET (XLEN-4) #define CSR_ICOUNT_TYPE_LENGTH 4 #define CSR_ICOUNT_TYPE (0xfULL << CSR_ICOUNT_TYPE_OFFSET) -#define CSR_ICOUNT_DMODE_OFFSET XLEN-5 +#define CSR_ICOUNT_DMODE_OFFSET (XLEN-5) #define CSR_ICOUNT_DMODE_LENGTH 1 #define CSR_ICOUNT_DMODE (0x1ULL << CSR_ICOUNT_DMODE_OFFSET) /* @@ -1007,14 +1007,14 @@ #define DMI_COMMAND_CONTROL (0xffffffU << DMI_COMMAND_CONTROL_OFFSET) #define DMI_ABSTRACTAUTO 0x18 /* -* When a bit in this field is 1, read or write accesses the corresponding {\tt progbuf} word +* When a bit in this field is 1, read or write accesses to the corresponding {\tt progbuf} word * cause the command in \Rcommand to be executed again. */ #define DMI_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET 16 #define DMI_ABSTRACTAUTO_AUTOEXECPROGBUF_LENGTH 16 #define DMI_ABSTRACTAUTO_AUTOEXECPROGBUF (0xffffU << DMI_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET) /* -* When a bit in this field is 1, read or write accesses the corresponding {\tt data} word +* When a bit in this field is 1, read or write accesses to the corresponding {\tt data} word * cause the command in \Rcommand to be executed again. */ #define DMI_ABSTRACTAUTO_AUTOEXECDATA_OFFSET 0 @@ -1043,15 +1043,15 @@ #define DMI_AUTHDATA_DATA (0xffffffffU << DMI_AUTHDATA_DATA_OFFSET) #define DMI_SBCS 0x38 /* -* When a 1 is written here, triggers a read at the address in {\tt -* sbaddress} using the access size set by \Fsbaccess. +* When a 1, every write to \Rsbaddresszero automatically triggers a +* system bus read at the new address. */ -#define DMI_SBCS_SBSINGLEREAD_OFFSET 20 -#define DMI_SBCS_SBSINGLEREAD_LENGTH 1 -#define DMI_SBCS_SBSINGLEREAD (0x1U << DMI_SBCS_SBSINGLEREAD_OFFSET) +#define DMI_SBCS_SBREADONADDR_OFFSET 20 +#define DMI_SBCS_SBREADONADDR_LENGTH 1 +#define DMI_SBCS_SBREADONADDR (0x1U << DMI_SBCS_SBREADONADDR_OFFSET) /* * Select the access size to use for system bus accesses triggered by -* writes to the {\tt sbaddress} registers or \Rsbdatazero. +* writes to \Rsbaddresszero or \Rsbdatazero. * * 0: 8-bit * @@ -1080,9 +1080,9 @@ * When 1, every read from \Rsbdatazero automatically triggers a * system bus read at the (possibly auto-incremented) address. */ -#define DMI_SBCS_SBAUTOREAD_OFFSET 15 -#define DMI_SBCS_SBAUTOREAD_LENGTH 1 -#define DMI_SBCS_SBAUTOREAD (0x1U << DMI_SBCS_SBAUTOREAD_OFFSET) +#define DMI_SBCS_SBREADONDATA_OFFSET 15 +#define DMI_SBCS_SBREADONDATA_LENGTH 1 +#define DMI_SBCS_SBREADONDATA (0x1U << DMI_SBCS_SBREADONDATA_OFFSET) /* * When the debug module's system bus * master causes a bus error, this field gets set. The bits in this |