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authorAndrew Waterman <andrew@sifive.com>2022-10-20 13:03:06 -0700
committerAndrew Waterman <andrew@sifive.com>2022-10-20 13:03:06 -0700
commitc10ad3c85af430d9cf0ddf656061f6e33993ff5b (patch)
tree44fc063077d9262713f7ae12fa8097d8b076f06b
parent6b689208d925200c9db203d107f6ffb9a3899d48 (diff)
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Use reg_t, not uint64_t, for address-like quantities
-rw-r--r--riscv/mmu.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h
index ca76894..1e5260b 100644
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -341,7 +341,7 @@ public:
return target_big_endian? target_endian<T>::to_be(n) : target_endian<T>::to_le(n);
}
- void set_cache_blocksz(uint64_t size)
+ void set_cache_blocksz(reg_t size)
{
blocksz = size;
}
@@ -352,7 +352,7 @@ private:
memtracer_list_t tracer;
reg_t load_reservation_address;
uint16_t fetch_temp;
- uint64_t blocksz;
+ reg_t blocksz;
// implement an instruction cache for simulator performance
icache_entry_t icache[ICACHE_ENTRIES];