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author | Chih-Min Chao <48193236+chihminchao@users.noreply.github.com> | 2020-07-09 03:34:31 +0800 |
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committer | GitHub <noreply@github.com> | 2020-07-08 12:34:31 -0700 |
commit | 26eb6a2cbc1dfa7edf43e04a858af0de7870e650 (patch) | |
tree | a127b1ff8bd31026c6063ad1b5f6f493bb6fb7ee | |
parent | 68eb54397e88488e40b937bb9f73a9078c7dbb46 (diff) | |
download | spike-26eb6a2cbc1dfa7edf43e04a858af0de7870e650.zip spike-26eb6a2cbc1dfa7edf43e04a858af0de7870e650.tar.gz spike-26eb6a2cbc1dfa7edf43e04a858af0de7870e650.tar.bz2 |
rvv: vstart register needs only lg2(VLEN) bits (#501)
As section 3.6 says:
The vstart CSR is defined to have only enough writable bits to hold
the largest element index (one less than the maximum VLMAX) or lg2(VLEN) bits.
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
-rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 9dc5911..b2b38d1 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -925,7 +925,7 @@ void processor_t::set_csr(int which, reg_t val) break; case CSR_VSTART: dirty_vs_state; - VU.vstart = val; + VU.vstart = val & (VU.get_vlen() - 1); break; case CSR_VXSAT: dirty_vs_state; |