diff options
| author | Andrew Waterman <andrew@sifive.com> | 2017-03-27 21:43:48 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-03-27 21:43:48 -0700 |
| commit | 7b396b51a6c38bc3472ea9c995e8015b39f19c1f (patch) | |
| tree | 7d62fcfbc7b8abd24dcb9ae1117592ed3c96277f | |
| parent | 8f4fb411b016846a539a1ff1cd645a555e3737be (diff) | |
| download | spike-7b396b51a6c38bc3472ea9c995e8015b39f19c1f.zip spike-7b396b51a6c38bc3472ea9c995e8015b39f19c1f.tar.gz spike-7b396b51a6c38bc3472ea9c995e8015b39f19c1f.tar.bz2 | |
Set badaddr=0 on illegal instruction traps
| -rw-r--r-- | riscv/decode.h | 6 | ||||
| -rw-r--r-- | riscv/extension.cc | 2 | ||||
| -rw-r--r-- | riscv/processor.cc | 4 | ||||
| -rw-r--r-- | riscv/trap.h | 2 |
4 files changed, 7 insertions, 7 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 061b5b6..bec548a 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -174,13 +174,13 @@ private: #define JUMP_TARGET (pc + insn.uj_imm()) #define RM ({ int rm = insn.rm(); \ if(rm == 7) rm = STATE.frm; \ - if(rm > 4) throw trap_illegal_instruction(); \ + if(rm > 4) throw trap_illegal_instruction(0); \ rm; }) #define get_field(reg, mask) (((reg) & (decltype(reg))(mask)) / ((mask) & ~((mask) << 1))) #define set_field(reg, mask, val) (((reg) & ~(decltype(reg))(mask)) | (((decltype(reg))(val) * ((mask) & ~((mask) << 1))) & (decltype(reg))(mask))) -#define require(x) if (unlikely(!(x))) throw trap_illegal_instruction() +#define require(x) if (unlikely(!(x))) throw trap_illegal_instruction(0) #define require_privilege(p) require(STATE.prv >= (p)) #define require_rv64 require(xlen == 64) #define require_rv32 require(xlen == 32) @@ -227,7 +227,7 @@ private: unsigned csr_priv = get_field((which), 0x300); \ unsigned csr_read_only = get_field((which), 0xC00) == 3; \ if (((write) && csr_read_only) || STATE.prv < csr_priv) \ - throw trap_illegal_instruction(); \ + throw trap_illegal_instruction(0); \ (which); }) #define DEBUG_START 0x100 diff --git a/riscv/extension.cc b/riscv/extension.cc index a34dd80..520c2ed 100644 --- a/riscv/extension.cc +++ b/riscv/extension.cc @@ -9,7 +9,7 @@ extension_t::~extension_t() void extension_t::illegal_instruction() { - throw trap_illegal_instruction(); + throw trap_illegal_instruction(0); } void extension_t::raise_interrupt() diff --git a/riscv/processor.cc b/riscv/processor.cc index f6b4cb6..3830b1e 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -604,12 +604,12 @@ reg_t processor_t::get_csr(int which) case CSR_DSCRATCH: return state.dscratch; } - throw trap_illegal_instruction(); + throw trap_illegal_instruction(0); } reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc) { - throw trap_illegal_instruction(); + throw trap_illegal_instruction(0); } insn_func_t processor_t::decode_insn(insn_t insn) diff --git a/riscv/trap.h b/riscv/trap.h index 20313e9..91e5223 100644 --- a/riscv/trap.h +++ b/riscv/trap.h @@ -46,7 +46,7 @@ class mem_trap_t : public trap_t DECLARE_MEM_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned) DECLARE_MEM_TRAP(CAUSE_FETCH_ACCESS, instruction_access_fault) -DECLARE_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction) +DECLARE_MEM_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction) DECLARE_MEM_TRAP(CAUSE_BREAKPOINT, breakpoint) DECLARE_MEM_TRAP(CAUSE_MISALIGNED_LOAD, load_address_misaligned) DECLARE_MEM_TRAP(CAUSE_MISALIGNED_STORE, store_address_misaligned) |