diff options
| author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2011-12-10 17:40:07 -0800 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2011-12-10 17:40:07 -0800 |
| commit | 2a6e490332f1b3c258b1e6aec190dc64761bf09a (patch) | |
| tree | c721a8ce465a9570f1760437899c8dc2223f9e4b | |
| parent | 8ce456c77b4f0159488b36c81a40c939c7d7f9e6 (diff) | |
| download | spike-2a6e490332f1b3c258b1e6aec190dc64761bf09a.zip spike-2a6e490332f1b3c258b1e6aec190dc64761bf09a.tar.gz spike-2a6e490332f1b3c258b1e6aec190dc64761bf09a.tar.bz2 | |
fix utidx assign bug, make ut code execute faster
| -rw-r--r-- | riscv/insns/vf.h | 2 | ||||
| -rw-r--r-- | riscv/processor.cc | 3 |
2 files changed, 3 insertions, 2 deletions
diff --git a/riscv/insns/vf.h b/riscv/insns/vf.h index d1527b3..270c6fd 100644 --- a/riscv/insns/vf.h +++ b/riscv/insns/vf.h @@ -5,5 +5,5 @@ for (int i=0; i<VL; i++) uts[i]->utmode = true; uts[i]->run = true; while (uts[i]->utmode) - uts[i]->step(1, false); // XXX + uts[i]->step(100, false); // XXX } diff --git a/riscv/processor.cc b/riscv/processor.cc index 99539f5..6df910c 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -20,10 +20,11 @@ processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id) processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id, uint32_t _utidx) - : sim(*_sim), mmu(*_mmu), id(_id), utidx(_utidx) + : sim(*_sim), mmu(*_mmu), id(_id) { reset(); set_sr(sr | SR_EF | SR_EV); + utidx = _utidx; // microthreads don't possess their own microthreads for (int i=0; i<MAX_UTS; i++) |