diff options
author | Andrew Waterman <waterman@eecs.berkeley.edu> | 2012-05-15 18:31:03 -0700 |
---|---|---|
committer | Andrew Waterman <waterman@eecs.berkeley.edu> | 2012-05-15 18:31:03 -0700 |
commit | 2183afefb8f8534ff43d76ea93d7ac0b0e060fc8 (patch) | |
tree | 43216d45251a3323b1ab24475bd7e64801e00894 | |
parent | 546ceaee914e8d87fbbfdb04f5923fe002a9b9c7 (diff) | |
download | spike-2183afefb8f8534ff43d76ea93d7ac0b0e060fc8.zip spike-2183afefb8f8534ff43d76ea93d7ac0b0e060fc8.tar.gz spike-2183afefb8f8534ff43d76ea93d7ac0b0e060fc8.tar.bz2 |
fix htif interaction with interactive mode
-rw-r--r-- | riscv/interactive.cc | 2 | ||||
-rw-r--r-- | riscv/sim.cc | 13 | ||||
-rw-r--r-- | riscv/sim.h | 5 |
3 files changed, 9 insertions, 11 deletions
diff --git a/riscv/interactive.cc b/riscv/interactive.cc index a81e2f2..5ba6d23 100644 --- a/riscv/interactive.cc +++ b/riscv/interactive.cc @@ -242,8 +242,6 @@ void sim_t::interactive_until(const std::string& cmd, const std::vector<std::str current = get_pc(args2); else if(scmd == "mem") current = get_mem(args2); - else if(scmd == "tohost") - current = tohost; else return; diff --git a/riscv/sim.cc b/riscv/sim.cc index 27933b7..8a56cd9 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -12,10 +12,9 @@ sim_t::sim_t(int _nprocs, htif_t* _htif) : htif(_htif), - tohost(0), - fromhost(0), procs(_nprocs), - running(false) + running(false), + steps(0) { // allocate target machine's memory, shrinking it as necessary // until the allocation succeeds @@ -69,7 +68,7 @@ void sim_t::run(bool debug) // word 1 of memory contains the core count mmu->store_uint32(4, num_cores()); - //htif->wait_for_start(); + htif->wait_for_start(); for(running = true; running; ) { @@ -82,8 +81,12 @@ void sim_t::run(bool debug) void sim_t::step_all(size_t n, size_t interleave, bool noisy) { - htif->wait_for_packet(); for(size_t j = 0; j < n; j+=interleave) + { + if (steps % 16384 + interleave >= 16384) + htif->wait_for_packet(); + steps += interleave; for(int i = 0; i < (int)num_cores(); i++) procs[i]->step(interleave,noisy); + } } diff --git a/riscv/sim.h b/riscv/sim.h index 8109b50..51e33d4 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -27,10 +27,6 @@ public: private: htif_t* htif; - // global registers for communication with host machine - reg_t tohost; - reg_t fromhost; - // main memory, shared between processors char* mem; size_t memsz; // memory size in bytes @@ -42,6 +38,7 @@ private: // terminate the simulation loop after the current iteration void stop() { running = false; } bool running; + size_t steps; // run each processor for n instructions; interleave instructions are // run on a processor before moving on to the next processor. |