diff options
| author | Andrew Waterman <andrew@sifive.com> | 2023-09-28 16:34:40 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-09-28 16:34:40 -0700 |
| commit | d1efcdffffee57bab0fdbd2b377c6132b37556fd (patch) | |
| tree | b80012034d67c4335f83bcfa47a9c5a49a7e7ec0 | |
| parent | 847fe5d59a5e198146eca6a3c69fe96b07dad5c6 (diff) | |
| parent | 77e9aaef19f528d8ced2301fe39eb941a9fdc3e2 (diff) | |
| download | spike-d1efcdffffee57bab0fdbd2b377c6132b37556fd.zip spike-d1efcdffffee57bab0fdbd2b377c6132b37556fd.tar.gz spike-d1efcdffffee57bab0fdbd2b377c6132b37556fd.tar.bz2 | |
Merge pull request #1473 from riscv-software-src/unavailable
Fix behavior of unavailable harts.
| -rw-r--r-- | riscv/debug_module.cc | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index 4a7a802..e9aef1a 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -413,14 +413,14 @@ bool debug_module_t::dmi_read(unsigned address, uint32_t *value) dmstatus.allresumeack = false; } auto hart = sim->get_harts().at(hart_id); - if (hart_state[hart_id].halted) { - dmstatus.allrunning = false; - dmstatus.anyhalted = true; - dmstatus.allunavail = false; - } else if (!hart_available(hart_id)) { + if (!hart_available(hart_id)) { dmstatus.allrunning = false; dmstatus.allhalted = false; dmstatus.anyunavail = true; + } else if (hart_state[hart_id].halted) { + dmstatus.allrunning = false; + dmstatus.anyhalted = true; + dmstatus.allunavail = false; } else { dmstatus.allhalted = false; dmstatus.anyrunning = true; @@ -579,6 +579,10 @@ bool debug_module_t::perform_abstract_command() abstractcs.cmderr = CMDERR_BUSY; return true; } + if (!hart_available(dmcontrol.hartsel)) { + abstractcs.cmderr = CMDERR_HALTRESUME; + return true; + } if ((command >> 24) == 0) { // register access |