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| author | Andrew Waterman <andrew@sifive.com> | 2026-01-27 17:12:22 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2026-01-27 17:12:22 -0800 |
| commit | 98ccf030bb02a029944cd938d5bcb73275350df4 (patch) | |
| tree | 015668aa848b49c5f00f67c575509e8a6969ee76 | |
| parent | 7655ac084339c2054cdd92657d17bf737742ece4 (diff) | |
| parent | 49d1d2a80294e921ad2a34536e78973234e2c7b9 (diff) | |
| download | spike-master.zip spike-master.tar.gz spike-master.tar.bz2 | |
Fix: Enforce virtual_instruction trap for VU-mode indirect CSR access
| -rw-r--r-- | riscv/csrs.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 249c76d..6424e03 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -1852,6 +1852,10 @@ sscsrind_reg_csr_t::sscsrind_reg_csr_t(processor_t* const proc, const reg_t addr } void sscsrind_reg_csr_t::verify_permissions(insn_t insn, bool write) const { + if (state->v && state->prv == PRV_U) { + throw trap_virtual_instruction(insn.bits()); + } + if (proc->extension_enabled(EXT_SMSTATEEN)) { if ((state->prv < PRV_M) && !(state->mstateen[0]->read() & MSTATEEN0_CSRIND)) throw trap_illegal_instruction(insn.bits()); |