From 1581f1737851f7e44dcf1eebbc52bdd6f1f7c9ca Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 9 Sep 2022 14:42:11 -0700 Subject: arm: dts: imx8mp-venice-gw74xx: add dsa phy handles to u-boot dtsi The upstream Linux DSA drivers do not require phy-handle nodes in the DSA ports yet the U-Boot DSA drivers do. Add a phy-handle and the mdio nodes to the u-boot.dtsi file so that future dts file syncrhonization between Linux and U-Boot don't break networking. Fixes: e0caa84ca685 ("imx8mp: synchronise device tree with linux") Signed-off-by: Tim Harvey --- arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi | 59 +++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi index 920246d..caf5d3a 100644 --- a/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi @@ -162,6 +162,65 @@ u-boot,dm-spl; }; +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + lan1: port@0 { + phy-handle = <&sw_phy0>; + }; + + lan2: port@1 { + phy-handle = <&sw_phy1>; + }; + + lan3: port@2 { + phy-handle = <&sw_phy2>; + }; + + lan4: port@3 { + phy-handle = <&sw_phy3>; + }; + + lan5: port@4 { + phy-handle = <&sw_phy4>; + }; + }; + + mdios { + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + reg = <0>; + compatible = "microchip,ksz-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + sw_phy0: ethernet-phy@0 { + reg = <0x0>; + }; + + sw_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + + sw_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + + sw_phy3: ethernet-phy@3 { + reg = <0x3>; + }; + + sw_phy4: ethernet-phy@4 { + reg = <0x4>; + }; + }; + }; +}; + &usdhc2 { assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; assigned-clock-rates = <400000000>; -- cgit v1.1 From 9bf0cbf396beaf3257698f672207ab7849134618 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 9 Sep 2022 14:42:38 -0700 Subject: arm: dts: imx8mm-venice-gw7901: add dsa phy handles to u-boot dtsi The upstream Linux DSA drivers do not require phy-handle nodes in the DSA ports yet the U-Boot DSA drivers do. Add a phy-handle and the mdio nodes to the u-boot.dtsi file so that future dts file syncrhonization between Linux and U-Boot don't break networking. Fixes: 24a7a3c1c042 ("imx8mm: synchronise device tree with linux") Signed-off-by: Tim Harvey --- arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi | 51 +++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi index 11c773b..dc99e7b 100644 --- a/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi @@ -129,6 +129,57 @@ phy-reset-post-delay = <1>; }; +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + lan1: port@0 { + phy-handle = <&sw_phy0>; + }; + + lan2: port@1 { + phy-handle = <&sw_phy1>; + }; + + lan3: port@2 { + phy-handle = <&sw_phy2>; + }; + + lan4: port@3 { + phy-handle = <&sw_phy3>; + }; + }; + + mdios { + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + reg = <0>; + compatible = "microchip,ksz-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + sw_phy0: ethernet-phy@0 { + reg = <0x0>; + }; + + sw_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + + sw_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + + sw_phy3: ethernet-phy@3 { + reg = <0x3>; + }; + }; + }; +}; + &pinctrl_fec1 { u-boot,dm-spl; }; -- cgit v1.1 From fdf6bbb260c36bb54826bffb4dd4d62b90c3cede Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 19 Sep 2022 21:37:07 +0200 Subject: ARM: imx: Deduplicate i.MX8M SNVS LPGPR unlock Pull this LPGPR unlock into common code, since it is used in multiple systems already. Signed-off-by: Marek Vasut --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 5 +++++ arch/arm/mach-imx/imx8m/soc.c | 12 ++++++++++++ .../imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c | 17 ----------------- board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c | 17 ----------------- board/menlo/mx8menlo/mx8menlo.c | 17 ----------------- 5 files changed, 17 insertions(+), 51 deletions(-) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index ff3b9dd..29d5baa 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -27,6 +27,7 @@ #define IOMUXC_GPR_BASE_ADDR 0x30340000 #define OCOTP_BASE_ADDR 0x30350000 #define ANATOP_BASE_ADDR 0x30360000 +#define SNVS_BASE_ADDR 0x30370000 #define CCM_BASE_ADDR 0x30380000 #define SRC_BASE_ADDR 0x30390000 #define GPC_BASE_ADDR 0x303A0000 @@ -113,6 +114,10 @@ #define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1) #define SRC_DDR1_RCR_PRESET_N_MASK BIT(0) +#define SNVS_LPSR 0x4c +#define SNVS_LPLVDR 0x64 +#define SNVS_LPPGDR_INIT 0x41736166 + struct iomuxc_gpr_base_regs { u32 gpr[47]; }; diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index d115b25..5739546 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -544,6 +544,16 @@ static int imx8m_check_clock(void *ctx, struct event *event) } EVENT_SPY(EVT_DM_POST_INIT, imx8m_check_clock); +static void imx8m_setup_snvs(void) +{ + /* Enable SNVS clock */ + clock_enable(CCGR_SNVS, 1); + /* Initialize glitch detect */ + writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR); + /* Clear interrupt status */ + writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR); +} + int arch_cpu_init(void) { struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; @@ -594,6 +604,8 @@ int arch_cpu_init(void) writel(0x200, &ocotp->ctrl_clr); } + imx8m_setup_snvs(); + return 0; } diff --git a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c index 6dc4e6a..dc08830 100644 --- a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c +++ b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c @@ -34,22 +34,6 @@ int board_phys_sdram_size(phys_size_t *size) return 0; } -/* IMX8M SNVS registers needed for the bootcount functionality */ -#define SNVS_BASE_ADDR 0x30370000 -#define SNVS_LPSR 0x4c -#define SNVS_LPLVDR 0x64 -#define SNVS_LPPGDR_INIT 0x41736166 - -static void setup_snvs(void) -{ - /* Enable SNVS clock */ - clock_enable(CCGR_SNVS, 1); - /* Initialize glitch detect */ - writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR); - /* Clear interrupt status */ - writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR); -} - static void setup_mac_address(void) { unsigned char enetaddr[6]; @@ -99,7 +83,6 @@ static void setup_boot_device(void) int board_init(void) { - setup_snvs(); return 0; } diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c index 6f06daf..9d8e19d 100644 --- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c +++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c @@ -37,22 +37,6 @@ int board_phys_sdram_size(phys_size_t *size) return 0; } -/* IMX8M SNVS registers needed for the bootcount functionality */ -#define SNVS_BASE_ADDR 0x30370000 -#define SNVS_LPSR 0x4c -#define SNVS_LPLVDR 0x64 -#define SNVS_LPPGDR_INIT 0x41736166 - -static void setup_snvs(void) -{ - /* Enable SNVS clock */ - clock_enable(CCGR_SNVS, 1); - /* Initialize glitch detect */ - writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR); - /* Clear interrupt status */ - writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR); -} - static void setup_eqos(void) { struct iomuxc_gpr_base_regs *gpr = @@ -145,7 +129,6 @@ int board_init(void) { setup_eqos(); setup_fec(); - setup_snvs(); return 0; } diff --git a/board/menlo/mx8menlo/mx8menlo.c b/board/menlo/mx8menlo/mx8menlo.c index 9d3708a..61fc4ec 100644 --- a/board/menlo/mx8menlo/mx8menlo.c +++ b/board/menlo/mx8menlo/mx8menlo.c @@ -12,24 +12,7 @@ #include #include -#define SNVS_BASE_ADDR 0x30370000 -#define SNVS_LPSR 0x4c -#define SNVS_LPLVDR 0x64 -#define SNVS_LPPGDR_INIT 0x41736166 - -static void setup_snvs(void) -{ - /* Enable SNVS clock */ - clock_enable(CCGR_SNVS, 1); - /* Initialize glitch detect */ - writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR); - /* Clear interrupt status */ - writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR); -} - void board_early_init(void) { init_uart_clk(1); - - setup_snvs(); } -- cgit v1.1 From 8b9d90d6349f99cb9d95584e65dc04f080720fbd Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 13 Aug 2022 09:03:10 -0300 Subject: mx8m: csf.sh: Fix the calculation of fit_block_size When running the script to sign SPL/U-Boot on a kontron-sl-mx8mm board, the fit_block_size was calculated as 0x1000 instead of 0x1020. Add an extra parenthesis pair to fix it. Signed-off-by: Fabio Estevam Reviewed-by: Marek Vasut --- doc/imx/habv4/csf_examples/mx8m/csf.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/imx/habv4/csf_examples/mx8m/csf.sh b/doc/imx/habv4/csf_examples/mx8m/csf.sh index 6898513..7d267a7 100644 --- a/doc/imx/habv4/csf_examples/mx8m/csf.sh +++ b/doc/imx/habv4/csf_examples/mx8m/csf.sh @@ -40,7 +40,7 @@ dd if=csf_spl.bin of=flash.bin bs=1 seek=${spl_dd_offset} conv=notrunc # fitImage tree fit_block_base=$(printf "0x%x" $(( $(sed -n "/CONFIG_SYS_TEXT_BASE=/ s@.*=@@p" .config) - $(sed -n "/CONFIG_FIT_EXTERNAL_OFFSET=/ s@.*=@@p" .config) - 0x200 - 0x40)) ) fit_block_offset=$(printf "0x%s" $(fdtget -t x u-boot.dtb /binman/imx-boot/uboot offset)) -fit_block_size=$(printf "0x%x" $(( ( $(fdtdump u-boot.itb 2>/dev/null | sed -n "/^...totalsize:/ s@.*\(0x[0-9a-f]\+\).*@\1@p") + 0x1000 - 0x1 ) & ~(0x1000 - 0x1) + 0x20 )) ) +fit_block_size=$(printf "0x%x" $(( ( ($(fdtdump u-boot.itb 2>/dev/null | sed -n "/^...totalsize:/ s@.*\(0x[0-9a-f]\+\).*@\1@p") + 0x1000 - 0x1 ) & ~(0x1000 - 0x1)) + 0x20 )) ) sed -i "/Blocks = / s@.*@ Blocks = $fit_block_base $fit_block_offset $fit_block_size \"flash.bin\", \\\\@" csf_fit.tmp # U-Boot -- cgit v1.1 From 1d8f4c85e3c04f596b0464542221b3507af0014e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 23 Aug 2022 22:09:34 -0300 Subject: kontron-sl-mx8mm: Let CONFIG_SPL_FIT_IMAGE_TINY be selected When CONFIG_IMX_HAB is selected the 'hab_status' command reports several error events, indicating that the BootROM failed to authenticate the SPL. After inspecting the content of the memory location that corresponds to the DTB load address, the content did not match with the DTB binary, showing that some kind of memory corruption/overlap occurred. Letting the CONFIG_SPL_FIT_IMAGE_TINY option to be selected causes the DTB to be properly placed into RAM and no more overlap occurs. With this change, the 'hab_status' command returns no more error events, which indicates that the BootROM succeeded to authenticate the SPL. Signed-off-by: Fabio Estevam Reviewed-by: Frieder Schrempf --- configs/kontron-sl-mx8mm_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig index 5387f65..f8589b0 100644 --- a/configs/kontron-sl-mx8mm_defconfig +++ b/configs/kontron-sl-mx8mm_defconfig @@ -39,7 +39,6 @@ CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 -# CONFIG_SPL_FIT_IMAGE_TINY is not set CONFIG_SPL_I2C=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_POWER=y -- cgit v1.1