From b53005cafc775ba95f88913569219924482ebddd Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 25 Mar 2024 10:52:30 -0300 Subject: phycore_pcl063: Drop leading zero from USB vendor number CONFIG_USB_GADGET_VENDOR_NUM is a 16-bit number, so remove the leading zero. Reported-by: Marek Vasut Signed-off-by: Fabio Estevam Reviewed-by: Marek Vasut --- configs/phycore_pcl063_defconfig | 2 +- configs/phycore_pcl063_ull_defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig index 6b00df1..017054a 100644 --- a/configs/phycore_pcl063_defconfig +++ b/configs/phycore_pcl063_defconfig @@ -63,7 +63,7 @@ CONFIG_USB=y CONFIG_SPL_USB_HOST=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Phytec" -CONFIG_USB_GADGET_VENDOR_NUM=0x01b67 +CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 CONFIG_USB_GADGET_PRODUCT_NUM=0x4fff CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y diff --git a/configs/phycore_pcl063_ull_defconfig b/configs/phycore_pcl063_ull_defconfig index 6195fcf..b3da43a 100644 --- a/configs/phycore_pcl063_ull_defconfig +++ b/configs/phycore_pcl063_ull_defconfig @@ -54,7 +54,7 @@ CONFIG_USB=y CONFIG_SPL_USB_HOST=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Phytec" -CONFIG_USB_GADGET_VENDOR_NUM=0x01b67 +CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 CONFIG_USB_GADGET_PRODUCT_NUM=0x4fff CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y -- cgit v1.1 From e11fad3e186e66db46276346c50fa5b640e196bf Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 25 Mar 2024 09:27:02 -0700 Subject: arm: dts: imx8mm-venice-gw7901: add digital I/O direction control GPIO's The GW7901 has GPIO's to configure the direction of its isolated digital I/O signals. Add the GPIO pinmux, line names, and hog configuration. Signed-off-by: Tim Harvey --- arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi index e68030e..9fa2194 100644 --- a/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi @@ -43,6 +43,20 @@ }; &gpio4 { + dig1ctl { + gpio-hog; + output-low; + gpios = <4 GPIO_ACTIVE_HIGH>; + line-name = "dig1_ctl"; + }; + + dig2ctl { + gpio-hog; + output-low; + gpios = <5 GPIO_ACTIVE_HIGH>; + line-name = "dig2_ctl"; + }; + uart3_rs232 { gpio-hog; output-high; -- cgit v1.1 From 77dd945b2ca3a19c0327d3666dd35eba772b7abd Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 25 Mar 2024 09:27:22 -0700 Subject: arm: dts: imx8m*-venice-gw72xx: add TPM device The GW71xx baseboard has a TPM that defined in the upstream dt however we need to ensure the GPIO reset line is de-asserted which we do in boot firmware with a gpio hog. Signed-off-by: Tim Harvey --- arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi | 7 +++++++ arch/arm/dts/imx8mp-venice-gw71xx-2x-u-boot.dtsi | 9 +++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi index b359233..07789c8 100644 --- a/arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi @@ -25,6 +25,13 @@ gpios = <9 GPIO_ACTIVE_HIGH>; line-name = "dio1"; }; + + tpm_rst { + gpio-hog; + output-high; + gpios = <11 GPIO_ACTIVE_HIGH>; + line-name = "tpm_rst#"; + }; }; &gpio4 { diff --git a/arch/arm/dts/imx8mp-venice-gw71xx-2x-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw71xx-2x-u-boot.dtsi index 5c33f8c..216a7a0 100644 --- a/arch/arm/dts/imx8mp-venice-gw71xx-2x-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-venice-gw71xx-2x-u-boot.dtsi @@ -4,6 +4,15 @@ */ #include "imx8mp-venice-gw702x-u-boot.dtsi" +&gpio1 { + tpm_rst { + gpio-hog; + output-high; + gpios = <11 GPIO_ACTIVE_HIGH>; + line-name = "tpm_rst#"; + }; +}; + &gpio4 { dio_1 { gpio-hog; -- cgit v1.1 From f8b874f5426dc006cb5b31690b94a50a85a3236b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 26 Mar 2024 09:19:49 -0300 Subject: imx8: Add a default reset_cpu() implementation Add a weak default reset_cpu() implementation just like it is done on arch/arm/mach-imx/cpu.c. This allows the removal of the empty reset_cpu() in several board files. Signed-off-by: Fabio Estevam Tested-by: Hiago De Franco # Toradex Colibri iMX8X --- arch/arm/mach-imx/imx8/cpu.c | 4 ++++ board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c | 11 ----------- board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c | 8 -------- board/congatec/cgtqmx8/cgtqmx8.c | 7 ------- board/freescale/imx8qm_mek/imx8qm_mek.c | 8 -------- board/freescale/imx8qxp_mek/imx8qxp_mek.c | 8 -------- board/toradex/apalis-imx8/apalis-imx8.c | 8 -------- board/toradex/colibri-imx8x/colibri-imx8x.c | 8 -------- 8 files changed, 4 insertions(+), 58 deletions(-) diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 0b91e44..6e64318 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -84,6 +84,10 @@ static char *get_reset_cause(void) } } +__weak void reset_cpu(void) +{ +} + int arch_cpu_init(void) { #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION) diff --git a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c index 8b4d730..56b7bdb 100644 --- a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c +++ b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c @@ -136,17 +136,6 @@ void detail_board_ddr_info(void) puts("\nDDR "); } -/* - * Board specific reset that is system reset. - */ -void reset_cpu(void) -{ - puts("SCI reboot request"); - - while (1) - putc('.'); -} - #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, struct bd_info *bd) { diff --git a/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c b/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c index 206ce7d..7f766a6 100644 --- a/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c +++ b/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c @@ -112,14 +112,6 @@ int board_init(void) return 0; } -/* - * Board specific reset that is system reset. - */ -void reset_cpu(void) -{ - /* TODO */ -} - int board_mmc_get_env_dev(int devno) { return devno; diff --git a/board/congatec/cgtqmx8/cgtqmx8.c b/board/congatec/cgtqmx8/cgtqmx8.c index 26189ff..3b01354 100644 --- a/board/congatec/cgtqmx8/cgtqmx8.c +++ b/board/congatec/cgtqmx8/cgtqmx8.c @@ -371,13 +371,6 @@ void detail_board_ddr_info(void) puts("\nDDR "); } -/* - * Board specific reset that is system reset. - */ -void reset_cpu(void) -{ - /* TODO */ -} #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, struct bd_info *bd) diff --git a/board/freescale/imx8qm_mek/imx8qm_mek.c b/board/freescale/imx8qm_mek/imx8qm_mek.c index d96d1d0..2b209c8 100644 --- a/board/freescale/imx8qm_mek/imx8qm_mek.c +++ b/board/freescale/imx8qm_mek/imx8qm_mek.c @@ -102,14 +102,6 @@ int board_init(void) return 0; } -/* - * Board specific reset that is system reset. - */ -void reset_cpu(void) -{ - /* TODO */ -} - #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, struct bd_info *bd) { diff --git a/board/freescale/imx8qxp_mek/imx8qxp_mek.c b/board/freescale/imx8qxp_mek/imx8qxp_mek.c index 516cefd..833bee5 100644 --- a/board/freescale/imx8qxp_mek/imx8qxp_mek.c +++ b/board/freescale/imx8qxp_mek/imx8qxp_mek.c @@ -126,14 +126,6 @@ int board_init(void) return 0; } -/* - * Board specific reset that is system reset. - */ -void reset_cpu(void) -{ - /* TODO */ -} - #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, struct bd_info *bd) { diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c index 49719f2..0f993e6 100644 --- a/board/toradex/apalis-imx8/apalis-imx8.c +++ b/board/toradex/apalis-imx8/apalis-imx8.c @@ -291,14 +291,6 @@ int board_init(void) return 0; } -/* - * Board specific reset that is system reset. - */ -void reset_cpu(void) -{ - /* TODO */ -} - #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) { diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c b/board/toradex/colibri-imx8x/colibri-imx8x.c index 6fc8076..a507d66 100644 --- a/board/toradex/colibri-imx8x/colibri-imx8x.c +++ b/board/toradex/colibri-imx8x/colibri-imx8x.c @@ -140,14 +140,6 @@ int board_init(void) return 0; } -/* - * Board specific reset that is system reset. - */ -void reset_cpu(void) -{ - /* TODO */ -} - #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) { -- cgit v1.1 From a7fdca901f2cbd5cf92b32cd8e4fb6c4ab18e592 Mon Sep 17 00:00:00 2001 From: Hiago De Franco Date: Wed, 27 Mar 2024 09:45:50 -0300 Subject: board: toradex: colibri-imx8x: Remove board_gpio_init On Colibri iMX8X, the gpio initialization and usage should be handled by the device tree, not by the colibri-imx8x.c code. Therefore, remove it. Signed-off-by: Hiago De Franco --- board/toradex/colibri-imx8x/colibri-imx8x.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c b/board/toradex/colibri-imx8x/colibri-imx8x.c index a507d66..3565785 100644 --- a/board/toradex/colibri-imx8x/colibri-imx8x.c +++ b/board/toradex/colibri-imx8x/colibri-imx8x.c @@ -93,15 +93,6 @@ int board_early_init_f(void) return 0; } -#if IS_ENABLED(CONFIG_DM_GPIO) -static void board_gpio_init(void) -{ - /* TODO */ -} -#else -static inline void board_gpio_init(void) {} -#endif - #if IS_ENABLED(CONFIG_FEC_MXC) #include @@ -128,8 +119,6 @@ static void select_dt_from_module_version(void) int board_init(void) { - board_gpio_init(); - if (IS_ENABLED(CONFIG_IMX_SNVS_SEC_SC_AUTO)) { int ret = snvs_security_sc_init(); -- cgit v1.1 From b0887832c7c9262097a05619007f5da564c84fd9 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 28 Mar 2024 10:45:08 +0800 Subject: imx: imx8mq_evk: convert to OF_UPSTREAM Convert i.MX8MQ EVK to OF_UPSTREAM Signed-off-by: Peng Fan --- arch/arm/dts/Makefile | 1 - arch/arm/dts/imx8mq-evk.dts | 712 ---------------------------------------- arch/arm/mach-imx/imx8m/Kconfig | 1 + configs/imx8mq_evk_defconfig | 2 +- 4 files changed, 2 insertions(+), 714 deletions(-) delete mode 100644 arch/arm/dts/imx8mq-evk.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d85a330..b76ee4d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1090,7 +1090,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mq-cm.dtb \ imx8mn-evk.dtb \ imx8mn-var-som-symphony.dtb \ - imx8mq-evk.dtb \ imx8mm-beacon-kit.dtb \ imx8mn-beacon-kit.dtb \ imx8mq-mnt-reform2.dtb \ diff --git a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts deleted file mode 100644 index 82387b9..0000000 --- a/arch/arm/dts/imx8mq-evk.dts +++ /dev/null @@ -1,712 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2017 NXP - * Copyright (C) 2017-2018 Pengutronix, Lucas Stach - */ - -/dts-v1/; - -#include "imx8mq.dtsi" - -/ { - model = "NXP i.MX8MQ EVK"; - compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; - - chosen { - stdout-path = &uart1; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x00000000 0x40000000 0 0xc0000000>; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - reg_pcie1: regulator-pcie { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie1_reg>; - regulator-name = "MPCIE_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usdhc2_vmmc: regulator-vsd-3v3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2>; - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - buck2_reg: regulator-buck2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_buck2>; - compatible = "regulator-gpio"; - regulator-name = "vdd_arm"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1000000>; - gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - states = <1000000 0x0 - 900000 0x1>; - regulator-boot-on; - regulator-always-on; - }; - - ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ir>; - linux,autosuspend-period = <125>; - }; - - audio_codec_bt_sco: audio-codec-bt-sco { - compatible = "linux,bt-sco"; - #sound-dai-cells = <1>; - }; - - wm8524: audio-codec { - #sound-dai-cells = <0>; - compatible = "wlf,wm8524"; - wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - }; - - sound-bt-sco { - compatible = "simple-audio-card"; - simple-audio-card,name = "bt-sco-audio"; - simple-audio-card,format = "dsp_a"; - simple-audio-card,bitclock-inversion; - simple-audio-card,frame-master = <&btcpu>; - simple-audio-card,bitclock-master = <&btcpu>; - - btcpu: simple-audio-card,cpu { - sound-dai = <&sai3>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <16>; - }; - - simple-audio-card,codec { - sound-dai = <&audio_codec_bt_sco 1>; - }; - }; - - sound-wm8524 { - compatible = "simple-audio-card"; - simple-audio-card,name = "wm8524-audio"; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&cpudai>; - simple-audio-card,bitclock-master = <&cpudai>; - simple-audio-card,widgets = - "Line", "Left Line Out Jack", - "Line", "Right Line Out Jack"; - simple-audio-card,routing = - "Left Line Out Jack", "LINEVOUTL", - "Right Line Out Jack", "LINEVOUTR"; - - cpudai: simple-audio-card,cpu { - sound-dai = <&sai2>; - }; - - link_codec: simple-audio-card,codec { - sound-dai = <&wm8524>; - clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; - }; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "imx-spdif"; - spdif-controller = <&spdif1>; - spdif-out; - spdif-in; - }; - - sound-hdmi-arc { - compatible = "fsl,imx-audio-spdif"; - model = "imx-hdmi-arc"; - spdif-controller = <&spdif2>; - spdif-in; - }; -}; - -&A53_0 { - cpu-supply = <&buck2_reg>; -}; - -&A53_1 { - cpu-supply = <&buck2_reg>; -}; - -&A53_2 { - cpu-supply = <&buck2_reg>; -}; - -&A53_3 { - cpu-supply = <&buck2_reg>; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - status = "okay"; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - /* - * On imx8mq B0 PLL can't be bypassed so low bus is 166M - */ - opp-166M { - opp-hz = /bits/ 64 <166935483>; - }; - - opp-800M { - opp-hz = /bits/ 64 <800000000>; - }; - }; -}; - -&dphy { - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - qca,disable-smarteee; - vddio-supply = <&vddh>; - - vddh: vddh-regulator { - }; - }; - }; -}; - -&gpio5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_reset>; - - wl-reg-on-hog { - gpio-hog; - gpios = <29 GPIO_ACTIVE_HIGH>; - output-high; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x8>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <1100000>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <1100000>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - sw3a_reg: sw3ab { - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <975000>; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1675000>; - regulator-max-microvolt = <1975000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1625000>; - regulator-max-microvolt = <1875000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3625000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; -}; - -&lcdif { - status = "okay"; -}; - -&mipi_dsi { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - panel@0 { - pinctrl-0 = <&pinctrl_mipi_dsi>; - pinctrl-names = "default"; - compatible = "raydium,rm67191"; - reg = <0>; - reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; - dsi-lanes = <4>; - - port { - panel_in: endpoint { - remote-endpoint = <&mipi_dsi_out>; - }; - }; - }; - - ports { - port@1 { - reg = <1>; - mipi_dsi_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, - <&clk IMX8MQ_CLK_PCIE1_AUX>, - <&clk IMX8MQ_CLK_PCIE1_PHY>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; - vph-supply = <&vgen5_reg>; - status = "okay"; -}; - -&pcie1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie1>; - reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, - <&clk IMX8MQ_CLK_PCIE2_AUX>, - <&clk IMX8MQ_CLK_PCIE2_PHY>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; - vpcie-supply = <®_pcie1>; - vph-supply = <&vgen5_reg>; - status = "okay"; -}; - -&pgc_gpu { - power-supply = <&sw1a_reg>; -}; - -&pgc_vpu { - power-supply = <&sw1c_reg>; -}; - -&qspi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi>; - status = "okay"; - - n25q256a: flash@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q256a", "jedec,spi-nor"; - spi-max-frequency = <29000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - }; -}; - -&sai2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>; - assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>; - assigned-clock-rates = <0>, <24576000>; - status = "okay"; -}; - -&sai3 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MQ_CLK_SAI3>; - assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&spdif1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif1>; - assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1>; - assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; -}; - -&spdif2 { - assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>; - assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usb3_phy1 { - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - vqmmc-supply = <&sw4_reg>; - bus-width = <8>; - non-removable; - no-sd; - no-sdio; - status = "okay"; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_buck2: vddarmgrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 - MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f - >; - }; - - pinctrl_ir: irgrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x4f - >; - }; - - pinctrl_mipi_dsi: mipidsigrp { - fsl,pins = < - MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16 - >; - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76 - MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16 - >; - }; - - pinctrl_pcie1: pcie1grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76 - MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16 - >; - }; - - pinctrl_pcie1_reg: pcie1reggrp { - fsl,pins = < - MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16 - >; - }; - - pinctrl_qspi: qspigrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 - MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 - MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 - MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 - MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 - MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 - >; - }; - - pinctrl_reg_usdhc2: regusdhc2gpiogrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 - MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 - MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 - MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 - MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 - MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 - MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 - MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 - >; - }; - - pinctrl_spdif1: spdif1grp { - fsl,pins = < - MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 - MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_wdog: wdog1grp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; - - pinctrl_wifi_reset: wifiresetgrp { - fsl,pins = < - MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 - >; - }; -}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 5db643c..6f68ee2 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -53,6 +53,7 @@ config TARGET_IMX8MQ_EVK select FSL_CAAM select ARCH_MISC_INIT select SPL_CRYPTO if SPL + imply OF_UPSTREAM config TARGET_IMX8MQ_PHANBELL bool "imx8mq_phanbell" diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index 941b845..3a2d88a 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -11,7 +11,7 @@ CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mq-evk" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mq-evk" CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_TARGET_IMX8MQ_EVK=y CONFIG_DM_RESET=y -- cgit v1.1 From 5ddd66565024cb851aff71cdd717318b3020eca3 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 28 Mar 2024 10:45:09 +0800 Subject: imx: imx8mm_evk: convert to OF_UPSTREAM Convert i.MX8MM EVK to OF_UPSTREAM Signed-off-by: Peng Fan --- arch/arm/dts/Makefile | 1 - arch/arm/dts/imx8mm-evk.dts | 128 -------- arch/arm/dts/imx8mm-evk.dtsi | 615 -------------------------------------- arch/arm/mach-imx/imx8m/Kconfig | 1 + configs/imx8mm_evk_defconfig | 2 +- configs/imx8mm_evk_fspi_defconfig | 2 +- 6 files changed, 3 insertions(+), 746 deletions(-) delete mode 100644 arch/arm/dts/imx8mm-evk.dts delete mode 100644 arch/arm/dts/imx8mm-evk.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b76ee4d..b799249 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1074,7 +1074,6 @@ dtb-$(CONFIG_ARCH_IMX8ULP) += \ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-data-modul-edm-sbc.dtb \ - imx8mm-evk.dtb \ imx8mm-icore-mx8mm-ctouch2.dtb \ imx8mm-icore-mx8mm-edimm2.2.dtb \ imx8mm-kontron-bl.dtb \ diff --git a/arch/arm/dts/imx8mm-evk.dts b/arch/arm/dts/imx8mm-evk.dts deleted file mode 100644 index a2b24d4..0000000 --- a/arch/arm/dts/imx8mm-evk.dts +++ /dev/null @@ -1,128 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019-2020 NXP - */ - -/dts-v1/; - -#include -#include "imx8mm-evk.dtsi" - -/ { - model = "FSL i.MX8MM EVK board"; - compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; - - aliases { - spi0 = &flexspi; - }; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-750M { - opp-hz = /bits/ 64 <750000000>; - }; - }; -}; - -&flexspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexspi>; - status = "okay"; - - flash@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <80000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - }; -}; - -&usdhc3 { - assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&iomuxc { - pinctrl_flexspi: flexspigrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 - MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 - MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 - MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 - MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 - MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi deleted file mode 100644 index 7d6317d..0000000 --- a/arch/arm/dts/imx8mm-evk.dtsi +++ /dev/null @@ -1,615 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2020 NXP - */ - -/dts-v1/; - -#include -#include -#include "imx8mm.dtsi" - -/ { - chosen { - stdout-path = &uart2; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_led>; - - status { - label = "status"; - gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - reg_pcie0: regulator-pcie { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0_reg>; - regulator-name = "MPCIE_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000 0>; - brightness-levels = <0 255>; - num-interpolated-steps = <255>; - default-brightness-level = <250>; - }; - - ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ir>; - linux,autosuspend-period = <125>; - }; - - audio_codec_bt_sco: audio-codec-bt-sco { - compatible = "linux,bt-sco"; - #sound-dai-cells = <1>; - }; - - wm8524: audio-codec { - #sound-dai-cells = <0>; - compatible = "wlf,wm8524"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_wlf>; - wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; - }; - - sound-bt-sco { - compatible = "simple-audio-card"; - simple-audio-card,name = "bt-sco-audio"; - simple-audio-card,format = "dsp_a"; - simple-audio-card,bitclock-inversion; - simple-audio-card,frame-master = <&btcpu>; - simple-audio-card,bitclock-master = <&btcpu>; - - btcpu: simple-audio-card,cpu { - sound-dai = <&sai2>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <16>; - }; - - simple-audio-card,codec { - sound-dai = <&audio_codec_bt_sco 1>; - }; - }; - - sound-wm8524 { - compatible = "simple-audio-card"; - simple-audio-card,name = "wm8524-audio"; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&cpudai>; - simple-audio-card,bitclock-master = <&cpudai>; - simple-audio-card,widgets = - "Line", "Left Line Out Jack", - "Line", "Right Line Out Jack"; - simple-audio-card,routing = - "Left Line Out Jack", "LINEVOUTL", - "Right Line Out Jack", "LINEVOUTR"; - - cpudai: simple-audio-card,cpu { - sound-dai = <&sai3>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <32>; - }; - - simple-audio-card,codec { - sound-dai = <&wm8524>; - clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; - }; - }; -}; - -&A53_0 { - cpu-supply = <&buck2_reg>; -}; - -&A53_1 { - cpu-supply = <&buck2_reg>; -}; - -&A53_2 { - cpu-supply = <&buck2_reg>; -}; - -&A53_3 { - cpu-supply = <&buck2_reg>; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - qca,disable-smarteee; - vddio-supply = <&vddio>; - - vddio: vddio-regulator { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - - #clock-cells = <0>; - clocks = <&osc_32k 0>; - clock-output-names = "clk-32k-out"; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - buck2_reg: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - buck3_reg: BUCK3 { - // BUCK5 in datasheet - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - // BUCK6 in datasheet - regulator-name = "buck4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5_reg: BUCK5 { - // BUCK7 in datasheet - regulator-name = "buck5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6_reg: BUCK6 { - // BUCK8 in datasheet - regulator-name = "buck6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - ptn5110: tcpc@50 { - compatible = "nxp,ptn5110"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_typec1>; - reg = <0x50>; - interrupt-parent = <&gpio2>; - interrupts = <11 8>; - status = "okay"; - - port { - typec1_dr_sw: endpoint { - remote-endpoint = <&usb1_drd_sw>; - }; - }; - - typec1_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - power-role = "dual"; - data-role = "dual"; - try-power-role = "sink"; - source-pdos = ; - sink-pdos = ; - op-sink-microwatt = <15000000>; - self-powered; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - pca6416: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&pcie_phy { - fsl,refclk-pad-mode = ; - fsl,tx-deemph-gen1 = <0x2d>; - fsl,tx-deemph-gen2 = <0xf>; - clocks = <&pcie0_refclk>; - status = "okay"; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; - assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_CTRL>; - assigned-clock-rates = <10000000>, <250000000>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, - <&clk IMX8MM_SYS_PLL2_250M>; - vpcie-supply = <®_pcie0>; - status = "okay"; -}; - -&sai2 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - assigned-clocks = <&clk IMX8MM_CLK_SAI2>; - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; -}; - -&sai3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MM_CLK_SAI3>; - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart2 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "otg"; - hnp-disable; - srp-disable; - adp-disable; - usb-role-switch; - disable-over-current; - samsung,picophy-pre-emp-curr-control = <3>; - samsung,picophy-dc-vol-level-adjust = <7>; - status = "okay"; - - port { - usb1_drd_sw: endpoint { - remote-endpoint = <&typec1_dr_sw>; - }; - }; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 - >; - }; - - pinctrl_gpio_led: gpioledgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 - >; - }; - - pinctrl_ir: irgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f - >; - }; - - pinctrl_gpio_wlf: gpiowlfgrp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 - MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 - >; - }; - - pinctrl_pcie0_reg: pcie0reggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41 - >; - }; - - pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 - MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 - MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 - MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 - MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 - MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 - MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 - >; - }; - - pinctrl_typec1: typec1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 - >; - }; - - pinctrl_backlight: backlightgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06 - >; - }; -}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 6f68ee2..dd139c1 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -79,6 +79,7 @@ config TARGET_IMX8MM_EVK select FSL_CAAM select ARCH_MISC_INIT select SPL_CRYPTO if SPL + imply OF_UPSTREAM config TARGET_IMX8MM_ICORE_MX8MM bool "Engicam i.Core MX8M Mini SOM" diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index b51e393..e41facd 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -8,7 +8,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x400000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-evk" CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_TARGET_IMX8MM_EVK=y CONFIG_SYS_MONITOR_LEN=524288 diff --git a/configs/imx8mm_evk_fspi_defconfig b/configs/imx8mm_evk_fspi_defconfig index 34e8071..3aaf7a4 100644 --- a/configs/imx8mm_evk_fspi_defconfig +++ b/configs/imx8mm_evk_fspi_defconfig @@ -11,7 +11,7 @@ CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x400000 CONFIG_IMX_CONFIG="board/freescale/imx8mm_evk/imximage-8mm-lpddr4-fspi.cfg" CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-evk" CONFIG_SPL_TEXT_BASE=0x7E2000 CONFIG_TARGET_IMX8MM_EVK=y CONFIG_SYS_MONITOR_LEN=524288 -- cgit v1.1 From 73d57e0aa45f85e41b5f736f8ad6705797d95622 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 28 Mar 2024 10:45:10 +0800 Subject: imx: imx8mn-evk: convert to OF_UPSTREAM Convert i.MX8MN-EVK and i.MX8MN-DDR4-EVK to OF_UPSTREAM Signed-off-by: Peng Fan --- arch/arm/dts/Makefile | 2 - arch/arm/dts/imx8mn-ddr4-evk.dts | 160 -------------------------------------- arch/arm/dts/imx8mn-evk.dts | 128 ------------------------------ arch/arm/mach-imx/imx8m/Kconfig | 2 + configs/imx8mn_ddr4_evk_defconfig | 2 +- configs/imx8mn_evk_defconfig | 2 +- 6 files changed, 4 insertions(+), 292 deletions(-) delete mode 100644 arch/arm/dts/imx8mn-ddr4-evk.dts delete mode 100644 arch/arm/dts/imx8mn-evk.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b799249..56623d0 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1085,9 +1085,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-verdin-wifi-dev.dtb \ imx8mn-bsh-smm-s2.dtb \ imx8mn-bsh-smm-s2pro.dtb \ - imx8mn-ddr4-evk.dtb \ imx8mq-cm.dtb \ - imx8mn-evk.dtb \ imx8mn-var-som-symphony.dtb \ imx8mm-beacon-kit.dtb \ imx8mn-beacon-kit.dtb \ diff --git a/arch/arm/dts/imx8mn-ddr4-evk.dts b/arch/arm/dts/imx8mn-ddr4-evk.dts deleted file mode 100644 index d8ce217..0000000 --- a/arch/arm/dts/imx8mn-ddr4-evk.dts +++ /dev/null @@ -1,160 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 NXP - */ - -/dts-v1/; - -#include "imx8mn.dtsi" -#include "imx8mn-evk.dtsi" - -/ { - model = "NXP i.MX8MNano DDR4 EVK board"; - compatible = "fsl,imx8mn-ddr4-evk", "fsl,imx8mn"; -}; - -&A53_0 { - cpu-supply = <&buck2_reg>; -}; - -&A53_1 { - cpu-supply = <&buck2_reg>; -}; - -&A53_2 { - cpu-supply = <&buck2_reg>; -}; - -&A53_3 { - cpu-supply = <&buck2_reg>; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-600M { - opp-hz = /bits/ 64 <600000000>; - }; - }; -}; - -&i2c1 { - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - - #clock-cells = <0>; - clocks = <&osc_32k 0>; - clock-output-names = "clk-32k-out"; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - buck2_reg: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - buck3_reg: BUCK3 { - // BUCK5 in datasheet - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - }; - - buck4_reg: BUCK4 { - // BUCK6 in datasheet - regulator-name = "buck4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5_reg: BUCK5 { - // BUCK7 in datasheet - regulator-name = "buck5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6_reg: BUCK6 { - // BUCK8 in datasheet - regulator-name = "buck6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; diff --git a/arch/arm/dts/imx8mn-evk.dts b/arch/arm/dts/imx8mn-evk.dts deleted file mode 100644 index 4eb467d..0000000 --- a/arch/arm/dts/imx8mn-evk.dts +++ /dev/null @@ -1,128 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 NXP - */ - -/dts-v1/; - -#include "imx8mn.dtsi" -#include "imx8mn-evk.dtsi" -#include - -/ { - model = "NXP i.MX8MNano EVK board"; - compatible = "fsl,imx8mn-evk", "fsl,imx8mn"; -}; - -&A53_0 { - cpu-supply = <&buck2>; -}; - -&A53_1 { - cpu-supply = <&buck2>; -}; - -&A53_2 { - cpu-supply = <&buck2>; -}; - -&A53_3 { - cpu-supply = <&buck2>; -}; - -&i2c1 { - pmic: pmic@25 { - compatible = "nxp,pca9450b"; - reg = <0x25>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - - regulators { - buck1: BUCK1{ - regulator-name = "VDD_SOC"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <950000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - buck2: BUCK2 { - regulator-name = "VDD_ARM_0V9"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; - }; - - buck4: BUCK4{ - regulator-name = "VDD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5: BUCK5{ - regulator-name = "VDD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6: BUCK6 { - regulator-name = "NVCC_DRAM_1V1"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: LDO1 { - regulator-name = "NVCC_SNVS_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2: LDO2 { - regulator-name = "VDD_SNVS_0V8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3: LDO3 { - regulator-name = "VDDA_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4: LDO4 { - regulator-name = "VDD_PHY_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5: LDO5 { - regulator-name = "NVCC_SD2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index dd139c1..cb8afce 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -151,6 +151,7 @@ config TARGET_IMX8MN_EVK select IMX8M_LPDDR4 select FSL_CAAM select SPL_CRYPTO if SPL + imply OF_UPSTREAM config TARGET_IMX8MN_DDR4_EVK bool "imx8mn DDR4 EVK board" @@ -159,6 +160,7 @@ config TARGET_IMX8MN_DDR4_EVK select IMX8M_DDR4 select FSL_CAAM select SPL_CRYPTO if SPL + imply OF_UPSTREAM config TARGET_IMX8MN_VENICE bool "Support Gateworks Venice iMX8M Nano module" diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig index 743dea5..56b8880 100644 --- a/configs/imx8mn_ddr4_evk_defconfig +++ b/configs/imx8mn_ddr4_evk_defconfig @@ -8,7 +8,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x400000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr4-evk" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mn-ddr4-evk" CONFIG_SPL_TEXT_BASE=0x912000 CONFIG_TARGET_IMX8MN_DDR4_EVK=y CONFIG_SYS_MONITOR_LEN=524288 diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig index 5098fe5..91b7586 100644 --- a/configs/imx8mn_evk_defconfig +++ b/configs/imx8mn_evk_defconfig @@ -8,7 +8,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x400000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mn-evk" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mn-evk" CONFIG_SPL_TEXT_BASE=0x912000 CONFIG_TARGET_IMX8MN_EVK=y CONFIG_SYS_MONITOR_LEN=524288 -- cgit v1.1 From 131d895f929fe5f7bbabdde1da1de816f9fbff07 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 28 Mar 2024 10:45:11 +0800 Subject: imx: imx8mp_evk: convert to OF_UPSTREAM Convert to OF_UPSTREAM for i.MX8MP EVK Signed-off-by: Peng Fan --- arch/arm/dts/Makefile | 1 - arch/arm/dts/imx8mp-evk.dts | 684 ---------------------------------------- arch/arm/mach-imx/imx8m/Kconfig | 1 + configs/imx8mp_evk_defconfig | 2 +- 4 files changed, 2 insertions(+), 686 deletions(-) delete mode 100644 arch/arm/dts/imx8mp-evk.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 56623d0..7b7788f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1101,7 +1101,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mp-dhcom-pdk2.dtb \ imx8mp-dhcom-pdk3.dtb \ imx8mp-dhcom-pdk3-overlay-rev100.dtbo \ - imx8mp-evk.dtb \ imx8mp-icore-mx8mp-edimm2.2.dtb \ imx8mp-msc-sm2s.dtb \ imx8mp-phyboard-pollux-rdk.dtb \ diff --git a/arch/arm/dts/imx8mp-evk.dts b/arch/arm/dts/imx8mp-evk.dts deleted file mode 100644 index 9f1469d..0000000 --- a/arch/arm/dts/imx8mp-evk.dts +++ /dev/null @@ -1,684 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 NXP - */ - -/dts-v1/; - -#include -#include "imx8mp.dtsi" - -/ { - model = "NXP i.MX8MPlus EVK board"; - compatible = "fsl,imx8mp-evk", "fsl,imx8mp"; - - chosen { - stdout-path = &uart2; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_led>; - - status { - label = "yellow:status"; - gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0xc0000000>, - <0x1 0x00000000 0 0xc0000000>; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - reg_can1_stby: regulator-can1-stby { - compatible = "regulator-fixed"; - regulator-name = "can1-stby"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_can2_stby: regulator-can2-stby { - compatible = "regulator-fixed"; - regulator-name = "can2-stby"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_pcie0: regulator-pcie { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0_reg>; - regulator-name = "MPCIE_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&A53_0 { - cpu-supply = <®_arm>; -}; - -&A53_1 { - cpu-supply = <®_arm>; -}; - -&A53_2 { - cpu-supply = <®_arm>; -}; - -&A53_3 { - cpu-supply = <®_arm>; -}; - -&eqos { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eqos>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - snps,force_thresh_dma_mode; - snps,mtl-tx-config = <&mtl_tx_setup>; - snps,mtl-rx-config = <&mtl_rx_setup>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - eee-broken-1000t; - reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - realtek,clkout-disable; - }; - }; - - mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <5>; - snps,tx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,priority = <0x1>; - }; - - queue1 { - snps,dcb-algorithm; - snps,priority = <0x2>; - }; - - queue2 { - snps,dcb-algorithm; - snps,priority = <0x4>; - }; - - queue3 { - snps,dcb-algorithm; - snps,priority = <0x8>; - }; - - queue4 { - snps,dcb-algorithm; - snps,priority = <0xf0>; - }; - }; - - mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <5>; - snps,rx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,priority = <0x1>; - snps,map-to-dma-channel = <0>; - }; - - queue1 { - snps,dcb-algorithm; - snps,priority = <0x2>; - snps,map-to-dma-channel = <1>; - }; - - queue2 { - snps,dcb-algorithm; - snps,priority = <0x4>; - snps,map-to-dma-channel = <2>; - }; - - queue3 { - snps,dcb-algorithm; - snps,priority = <0x8>; - snps,map-to-dma-channel = <3>; - }; - - queue4 { - snps,dcb-algorithm; - snps,priority = <0xf0>; - snps,map-to-dma-channel = <4>; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy1>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - eee-broken-1000t; - reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - realtek,clkout-disable; - }; - }; -}; - -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can1_stby>; - status = "okay"; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can2_stby>; - status = "disabled";/* can2 pin conflict with pdm */ -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@25 { - compatible = "nxp,pca9450c"; - reg = <0x25>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - - regulators { - BUCK1 { - regulator-name = "BUCK1"; - regulator-min-microvolt = <720000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - reg_arm: BUCK2 { - regulator-name = "BUCK2"; - regulator-min-microvolt = <720000>; - regulator-max-microvolt = <1025000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; - }; - - BUCK4 { - regulator-name = "BUCK4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3600000>; - regulator-boot-on; - regulator-always-on; - }; - - BUCK5 { - regulator-name = "BUCK5"; - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1950000>; - regulator-boot-on; - regulator-always-on; - }; - - BUCK6 { - regulator-name = "BUCK6"; - regulator-min-microvolt = <1045000>; - regulator-max-microvolt = <1155000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1950000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO3 { - regulator-name = "LDO3"; - regulator-min-microvolt = <1710000>; - regulator-max-microvolt = <1890000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO5 { - regulator-name = "LDO5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - pca6416: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pca6416_int>; - interrupt-parent = <&gpio1>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - gpio-line-names = "EXT_PWREN1", - "EXT_PWREN2", - "CAN1/I2C5_SEL", - "PDM/CAN2_SEL", - "FAN_EN", - "PWR_MEAS_IO1", - "PWR_MEAS_IO2", - "EXP_P0_7", - "EXP_P1_0", - "EXP_P1_1", - "EXP_P1_2", - "EXP_P1_3", - "EXP_P1_4", - "EXP_P1_5", - "EXP_P1_6", - "EXP_P1_7"; - }; -}; - -/* I2C on expansion connector J22. */ -&i2c5 { - clock-frequency = <100000>; /* Lower clock speed for external bus. */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c5>; - status = "disabled"; /* can1 pins conflict with i2c5 */ - - /* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions: - * LOW: CAN1 (default, pull-down) - * HIGH: I2C5 - * You need to set it to high to enable I2C5 (for example, add gpio-hog - * in pca6416 node). - */ -}; - -&pcie_phy { - fsl,refclk-pad-mode = ; - clocks = <&pcie0_refclk>; - clock-names = "ref"; - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, - <&clk IMX8MP_CLK_PCIE_ROOT>, - <&clk IMX8MP_CLK_HSIO_AXI>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; - assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; - assigned-clock-rates = <10000000>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; - vpcie-supply = <®_pcie0>; - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart2 { - /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usb3_phy1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&usb_dwc3_1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1_vbus>; - dr_mode = "host"; - status = "okay"; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - bus-width = <4>; - status = "okay"; -}; - -&usdhc3 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_eqos: eqosgrp { - fsl,pins = < - MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 - MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 - MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 - MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 - MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 - MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 - MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 - MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 - MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 - MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 - MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 - MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 - MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 - MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 - MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 - MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 - MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 - MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 - MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 - MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 - MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 - MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 - MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 - MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 - MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 - MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 - MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 - MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 - MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 - MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 - MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 - >; - }; - - pinctrl_flexcan1_reg: flexcan1reggrp { - fsl,pins = < - MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ - >; - }; - - pinctrl_flexcan2_reg: flexcan2reggrp { - fsl,pins = < - MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ - >; - }; - - pinctrl_gpio_led: gpioledgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 - MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 - MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 - >; - }; - - pinctrl_i2c5: i2c5grp { - fsl,pins = < - MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2 - MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2 - >; - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = < - MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 /* open drain, pull up */ - MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41 - >; - }; - - pinctrl_pcie0_reg: pcie0reggrp { - fsl,pins = < - MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 - >; - }; - - pinctrl_pca6416_int: pca6416_int_grp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* Input pull-up. */ - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 - MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 - >; - }; - - pinctrl_usb1_vbus: usb1grp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 - >; - }; -}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index cb8afce..fbde476 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -222,6 +222,7 @@ config TARGET_IMX8MP_EVK select FSL_CAAM select ARCH_MISC_INIT select SPL_CRYPTO if SPL + imply OF_UPSTREAM config TARGET_IMX8MP_VENICE bool "Support Gateworks Venice iMX8M Plus module" diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index 2846faa..7e5dfce 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -8,7 +8,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x400000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-evk" CONFIG_SPL_TEXT_BASE=0x920000 CONFIG_TARGET_IMX8MP_EVK=y CONFIG_SYS_MONITOR_LEN=524288 -- cgit v1.1 From b9edc1ec86558bf056c8f75db5b48a8ca5adaf4c Mon Sep 17 00:00:00 2001 From: Emanuele Ghidoli Date: Thu, 28 Mar 2024 11:30:12 +0100 Subject: crypto/fsl: allow accessing Job Ring from non-TrustZone Add a new kconfig option to allow non-secure world access to the CAAM Job Ring. This is needed, for example, when running linux without OP-TEE services, as it's done on Colibri iMX7. Fixes: 51f1357f3428 ("Revert "drivers/crypto/fsl: assign job-rings to non-TrustZone"") Signed-off-by: Emanuele Ghidoli --- drivers/crypto/fsl/Kconfig | 6 ++++++ drivers/crypto/fsl/jr.c | 19 +++++++++++++++++++ drivers/crypto/fsl/jr.h | 2 ++ 3 files changed, 27 insertions(+) diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig index eaad196..294e1c8 100644 --- a/drivers/crypto/fsl/Kconfig +++ b/drivers/crypto/fsl/Kconfig @@ -62,6 +62,12 @@ config SYS_FSL_SEC_LE if FSL_CAAM +config FSL_CAAM_JR_NTZ_ACCESS + bool "Give CAAM Job Ring access to non-secure world" + help + It is needed when OP-TEE is not used and Freescale CAAM Job Ring linux + driver is used. + config FSL_CAAM_RNG bool "Enable Random Number Generator support" depends on DM_RNG diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index ceb66dd..203f162 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -673,6 +673,21 @@ static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec) return ret; } +#if CONFIG_IS_ENABLED(FSL_CAAM_JR_NTZ_ACCESS) +static void jr_setown_non_trusted(ccsr_sec_t *sec) +{ + u32 jrown_ns; + int i; + + /* Set ownership of job rings to non-TrustZone mode */ + for (i = 0; i < ARRAY_SIZE(sec->jrliodnr); i++) { + jrown_ns = sec_in32(&sec->jrliodnr[i].ms); + jrown_ns |= JROWN_NS | JRMID_NS; + sec_out32(&sec->jrliodnr[i].ms, jrown_ns); + } +} +#endif + int sec_init_idx(uint8_t sec_idx) { int ret = 0; @@ -761,6 +776,10 @@ int sec_init_idx(uint8_t sec_idx) #if CONFIG_IS_ENABLED(OF_CONTROL) init: #endif +#if CONFIG_IS_ENABLED(FSL_CAAM_JR_NTZ_ACCESS) + jr_setown_non_trusted(sec); +#endif + ret = jr_init(sec_idx, caam); if (ret < 0) { printf("SEC%u: initialization failed\n", sec_idx); diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index 4e4c4af..b136cd8 100644 --- a/drivers/crypto/fsl/jr.h +++ b/drivers/crypto/fsl/jr.h @@ -37,6 +37,8 @@ #define JRNSLIODN_MASK 0x0fff0000 #define JRSLIODN_SHIFT 0 #define JRSLIODN_MASK 0x00000fff +#define JROWN_NS 0x00000008 +#define JRMID_NS 0x00000001 #define JRDID_MS_PRIM_DID BIT(0) #define JRDID_MS_PRIM_TZ BIT(4) -- cgit v1.1 From 81572004c78ffb70537b34921bf67da51602d711 Mon Sep 17 00:00:00 2001 From: Emanuele Ghidoli Date: Thu, 28 Mar 2024 11:30:13 +0100 Subject: configs: colibri-imx7: set non-secure boot mode as default Linux kernel is supposed to run in non-secure world, fix the defconfig accordingly. Signed-off-by: Emanuele Ghidoli --- configs/colibri_imx7_emmc_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig index 9d4423c..8dd9fe6 100644 --- a/configs/colibri_imx7_emmc_defconfig +++ b/configs/colibri_imx7_emmc_defconfig @@ -8,7 +8,6 @@ CONFIG_DEFAULT_DEVICE_TREE="imx7d-colibri-emmc-eval-v3" CONFIG_TARGET_COLIBRI_IMX7=y CONFIG_TARGET_COLIBRI_IMX7_EMMC=y CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y CONFIG_IMX_HAB=y -- cgit v1.1 From 06e04a97df6e110a624d62d6e80ed37c2f92e9f7 Mon Sep 17 00:00:00 2001 From: Emanuele Ghidoli Date: Thu, 28 Mar 2024 11:30:14 +0100 Subject: configs: colibri-imx7: allow accessing job-rings from non-TrustZone Set FSL_CAAM_JR_NTZ_ACCESS configuration since colibri-imx7 uses Freescale CAAM Job Ring linux driver Signed-off-by: Emanuele Ghidoli --- configs/colibri_imx7_defconfig | 1 + configs/colibri_imx7_emmc_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index 0c6a272..16f923b 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -72,6 +72,7 @@ CONFIG_SERVERIP="192.168.10.1" CONFIG_BOUNCE_BUFFER=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y +CONFIG_FSL_CAAM_JR_NTZ_ACCESS=y CONFIG_DFU_NAND=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x81100000 diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig index 8dd9fe6..7c6a725 100644 --- a/configs/colibri_imx7_emmc_defconfig +++ b/configs/colibri_imx7_emmc_defconfig @@ -61,6 +61,7 @@ CONFIG_USE_SERVERIP=y CONFIG_SERVERIP="192.168.10.1" CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y +CONFIG_FSL_CAAM_JR_NTZ_ACCESS=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x81100000 CONFIG_FASTBOOT_FLASH=y -- cgit v1.1 From f6ee245cabc470f8f9f51fd49c264aa31e7340ed Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 28 Mar 2024 18:49:18 +0800 Subject: arm: imx9: Fix MMU map table overlap The size for flexspi AHB buffer space is wrong, so correct it. Signed-off-by: Ye Li --- arch/arm/mach-imx/imx9/soc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index f06339f..e2794d6 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -262,7 +262,7 @@ static struct mm_region imx93_mem_map[] = { /* Flexible Serial Peripheral Interface */ .virt = 0x28000000UL, .phys = 0x28000000UL, - .size = 0x30000000UL, + .size = 0x08000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN -- cgit v1.1 From 6a9de676f5c7a3764553588da6976e5cde44164f Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 28 Mar 2024 18:49:59 +0800 Subject: thermal: imx_tmu: Fix TMU error on iMX8MQ imx_tmu_arch_init does not implement for iMX8MQ, error is returned Signed-off-by: Ye Li --- drivers/thermal/imx_tmu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/thermal/imx_tmu.c b/drivers/thermal/imx_tmu.c index c7fe0f0..ea6c832 100644 --- a/drivers/thermal/imx_tmu.c +++ b/drivers/thermal/imx_tmu.c @@ -402,6 +402,7 @@ static inline void imx_tmu_mx8mp_init(struct udevice *dev) { } #endif static inline void imx_tmu_mx93_init(struct udevice *dev) { } +static inline void imx_tmu_mx8mq_init(struct udevice *dev) { } static void imx_tmu_arch_init(struct udevice *dev) { @@ -411,6 +412,8 @@ static void imx_tmu_arch_init(struct udevice *dev) imx_tmu_mx8mp_init(dev); else if (is_imx93()) imx_tmu_mx93_init(dev); + else if (is_imx8mq()) + imx_tmu_mx8mq_init(dev); else dev_err(dev, "Unsupported SoC, TMU calibration not loaded!\n"); } -- cgit v1.1 From 6cd789c7fd6274b28432caa145e4c857de04c016 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 28 Mar 2024 18:50:55 +0800 Subject: image-container: Fix incorrect return value The spl_spi_get_uboot_offs weak function is defined unsigned int. Signed-off-by: Ye Li --- arch/arm/mach-imx/image-container.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c index c9455fe..35da0ae 100644 --- a/arch/arm/mach-imx/image-container.c +++ b/arch/arm/mach-imx/image-container.c @@ -262,7 +262,7 @@ static int get_imageset_end(void *dev, int dev_type) } #ifdef CONFIG_SPL_SPI_LOAD -unsigned long spl_spi_get_uboot_offs(struct spi_flash *flash) +unsigned int spl_spi_get_uboot_offs(struct spi_flash *flash) { int end; -- cgit v1.1 From 9dc7d5270beb4be24395deefd52f245441780959 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 28 Mar 2024 18:57:59 +0800 Subject: net: fec_mxc: Avoid enable regulator failure Change to regulator_set_enable_if_allowed to avoid enable failure, in case same phy supply shared by multiple FEC controllers. Signed-off-by: Ye Li --- drivers/net/fec_mxc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index ac93767..90af18f 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -1310,7 +1310,7 @@ static int fecmxc_probe(struct udevice *dev) #ifdef CONFIG_DM_REGULATOR if (priv->phy_supply) { - ret = regulator_set_enable(priv->phy_supply, true); + ret = regulator_set_enable_if_allowed(priv->phy_supply, true); if (ret) { printf("%s: Error enabling phy supply\n", dev->name); return ret; -- cgit v1.1 From 13cca97251ab1a1dd3990caa417faa6dd31387e4 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 28 Mar 2024 15:43:19 -0300 Subject: imx8mq_evk: Remove FEC and Ethernet PHY board code With Ethernet DM in place, there is no longer the need for having the board_phy_config() and setup_fec() functions anymore. Remove them. Successfully tested a TFTP transfer after these changes. Signed-off-by: Fabio Estevam --- board/freescale/imx8mq_evk/imx8mq_evk.c | 30 ------------------------------ 1 file changed, 30 deletions(-) diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.c b/board/freescale/imx8mq_evk/imx8mq_evk.c index e394805..e577e4d 100644 --- a/board/freescale/imx8mq_evk/imx8mq_evk.c +++ b/board/freescale/imx8mq_evk/imx8mq_evk.c @@ -54,38 +54,8 @@ int board_early_init_f(void) return 0; } -#ifdef CONFIG_FEC_MXC -static int setup_fec(void) -{ - struct iomuxc_gpr_base_regs *gpr = - (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; - - /* Use 125M anatop REF_CLK1 for ENET1, not from external */ - clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0); - return set_clk_enet(ENET_125MHZ); -} - -int board_phy_config(struct phy_device *phydev) -{ - /* enable rgmii rxc skew and phy mode select to RGMII copper */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); - - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); - - if (phydev->drv->config) - phydev->drv->config(phydev); - return 0; -} -#endif - int board_init(void) { -#ifdef CONFIG_FEC_MXC - setup_fec(); -#endif - #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_DWC3) init_usb_clk(); #endif -- cgit v1.1 From 5bc7bc60e9e63675e98514024a65a94bb97a4182 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Fri, 29 Mar 2024 12:18:06 +0100 Subject: arm: spl: xea: Remove I2S pins configuration from early initialization XEA is not supporting and using I2S codec, so there is no need to configure pins for it. Signed-off-by: Lukasz Majewski --- board/liebherr/xea/spl_xea.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/board/liebherr/xea/spl_xea.c b/board/liebherr/xea/spl_xea.c index df354ca..551ed6f 100644 --- a/board/liebherr/xea/spl_xea.c +++ b/board/liebherr/xea/spl_xea.c @@ -112,13 +112,6 @@ const iomux_cfg_t iomux_setup[] = { MX28_PAD_I2C0_SCL__I2C0_SCL, MX28_PAD_I2C0_SDA__I2C0_SDA, - /* I2S Codec */ - MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK, - MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK, - MX28_PAD_SAIF0_MCLK__SAIF0_MCLK, - MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0, - MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0, - /* PWR-Hold */ MX28_PAD_SPDIF__GPIO_3_27, -- cgit v1.1 From 3603e64003c3743fa5bc4dbf2a50f898e972ba01 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Fri, 29 Mar 2024 12:18:07 +0100 Subject: arm: spl: Add definition for PHY reset GPIO for XEA HW rev. 2 The imx287 based XEA board's revision 2 uses GPIO_3_21 for PHY reset It is safe to keep the GPIO_2_13 as well, as in the SPL SPI1 is not used for transmission. This simplifies the code, as the proper configuration is performed either in falcon boot's read DTB or in u-boot proper (with correct FIT configuration chosen). Signed-off-by: Lukasz Majewski --- board/liebherr/xea/spl_xea.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/liebherr/xea/spl_xea.c b/board/liebherr/xea/spl_xea.c index 551ed6f..4068a2a 100644 --- a/board/liebherr/xea/spl_xea.c +++ b/board/liebherr/xea/spl_xea.c @@ -225,7 +225,8 @@ const iomux_cfg_t iomux_setup[] = { MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET, - MX28_PAD_SSP1_CMD__GPIO_2_13, /* PHY reset */ + MX28_PAD_SSP1_CMD__GPIO_2_13, /* PHY reset HW Rev. 1*/ + MX28_PAD_SAIF0_LRCLK__GPIO_3_21, /* PHY reset HW Rev. 2*/ /* TIVA boot control */ MX28_PAD_GPMI_RDY3__GPIO_0_23 | MUX_CONFIG_BOOT, /* TIVA0 */ -- cgit v1.1 From 7e1b8d8f1e688e7f359bff76dd30232b02635062 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Fri, 29 Mar 2024 12:18:08 +0100 Subject: arm: xea: Add support for reading SoM (CPU) board HW revision The XEA board now has several HW revisions for SoM boards. This patch provides support for reading this revision ID values in early u-boot proper as production devices boot via falcon boot with correct DTB flashed at production (so there is no need to alter SPL). Additionally, the maximal SPL size (~55KiB) constraint is not allowing having even simplified FIT support in it. As a result it was necessary to handle reading GPIOs values solely in u-boot proper as one configuration (i.e. 'single binary' - imx28_xea_sb_defconfig) is not using SPL framework. Moreover, the 'board_som_rev' environment variable will be used to point correct configuration from the Linux FIT file. Additionally, as now XEA has its second HW revision - this information is printed when u-boot proper starts. Signed-off-by: Lukasz Majewski --- board/liebherr/xea/spl_xea.c | 11 ++++++++++ board/liebherr/xea/xea.c | 49 ++++++++++++++++++++++++++++++++++++++++++ configs/imx28_xea_defconfig | 1 + configs/imx28_xea_sb_defconfig | 1 + 4 files changed, 62 insertions(+) diff --git a/board/liebherr/xea/spl_xea.c b/board/liebherr/xea/spl_xea.c index 4068a2a..6cf8f83 100644 --- a/board/liebherr/xea/spl_xea.c +++ b/board/liebherr/xea/spl_xea.c @@ -231,6 +231,17 @@ const iomux_cfg_t iomux_setup[] = { /* TIVA boot control */ MX28_PAD_GPMI_RDY3__GPIO_0_23 | MUX_CONFIG_BOOT, /* TIVA0 */ MX28_PAD_GPMI_WRN__GPIO_0_25 | MUX_CONFIG_BOOT, /* TIVA1 */ + + /* HW revision ID Base Board */ + MX28_PAD_LCD_D12__GPIO_1_12, + MX28_PAD_LCD_D13__GPIO_1_13, + MX28_PAD_LCD_D14__GPIO_1_14, + + /* HW revision ID (SoM) */ + MX28_PAD_LCD_D15__GPIO_1_15, + MX28_PAD_LCD_D16__GPIO_1_16, + MX28_PAD_LCD_D17__GPIO_1_17, + MX28_PAD_LCD_D18__GPIO_1_18, }; u32 mxs_dram_vals[] = { diff --git a/board/liebherr/xea/xea.c b/board/liebherr/xea/xea.c index c8ac526..0a6fd7f 100644 --- a/board/liebherr/xea/xea.c +++ b/board/liebherr/xea/xea.c @@ -216,6 +216,34 @@ int spl_start_uboot(void) return !boot_tiva0 || !boot_tiva1; } #else +/* + * Reading the HW ID number for XEA SoM module + * + * GPIOs from Port 1 (GPIO1_15, GPIO1_16, GPIO1_17 and GPIO1_18) + * are used to store HW revision information. + * Reading of GPIOs values is performed before the Device Model is + * bring up as the proper DTB needs to be chosen first. + * + * Moreover, this approach is required as "single binary" configuration + * of U-Boot (imx28_xea_sb_defconfig) is NOT using SPL framework, so + * only minimal subset of functionality is provided when ID is read. + * + * Hence, the direct registers' access. + */ +#define XEA_SOM_HW_ID_GPIO_PORT (MXS_PINCTRL_BASE + (0x0900 + ((1) * 0x10))) +#define XEA_SOM_REV_MASK GENMASK(18, 15) +#define XEA_SOM_REV_SHIFT 15 + +static u8 get_som_rev(void) +{ + struct mxs_register_32 *reg = + (struct mxs_register_32 *)XEA_SOM_HW_ID_GPIO_PORT; + + u32 tmp = ~readl(®->reg); + u8 id = (tmp & XEA_SOM_REV_MASK) >> XEA_SOM_REV_SHIFT; + + return id; +} int board_early_init_f(void) { @@ -253,6 +281,27 @@ int board_init(void) return 0; } +#if defined(CONFIG_BOARD_LATE_INIT) +int board_late_init(void) +{ + int ret = env_set_ulong("board_som_rev", get_som_rev()); + + if (ret) + printf("Cannot set XEA's SoM revision env variable!\n"); + + return 0; +} +#endif + +#if defined(CONFIG_DISPLAY_BOARDINFO) +int checkboard(void) +{ + printf("Board: LWE XEA SoM HW rev %d\n", get_som_rev()); + + return 0; +} +#endif + int dram_init(void) { return mxs_dram_init(); diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig index 64a0561..6098c1f 100644 --- a/configs/imx28_xea_defconfig +++ b/configs/imx28_xea_defconfig @@ -39,6 +39,7 @@ CONFIG_BOOTCOMMAND="run ${bootpri} ; run ${bootsec}" CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="run prebootcmd" CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set diff --git a/configs/imx28_xea_sb_defconfig b/configs/imx28_xea_sb_defconfig index 9872d35..8d48d8c 100644 --- a/configs/imx28_xea_sb_defconfig +++ b/configs/imx28_xea_sb_defconfig @@ -23,6 +23,7 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200n8" CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="run prebootcmd" CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y # CONFIG_SPL_FRAMEWORK is not set CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y -- cgit v1.1 From f21b3e2cd954634d405fb522198d099879f3f1e7 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Fri, 29 Mar 2024 12:18:09 +0100 Subject: config: xea: Add limits for SPL and u-boot proper sizes The XEA board has following hard constraints regarding size of binaries: - u-boot.sb < 48 KiB - u-boot.img < 448 KiB Added values are supposed to avoid exceeding size of binaries during future u-boot development. Signed-off-by: Lukasz Majewski --- configs/imx28_xea_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig index 6098c1f..822a329 100644 --- a/configs/imx28_xea_defconfig +++ b/configs/imx28_xea_defconfig @@ -21,12 +21,15 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x20000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000 +CONFIG_SPL_SIZE_LIMIT=0xa000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x90000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x42000000 CONFIG_SPL_PAYLOAD="u-boot.img" +CONFIG_HAS_BOARD_SIZE_LIMIT=y +CONFIG_BOARD_SIZE_LIMIT=458752 CONFIG_TIMESTAMP=y CONFIG_FIT=y # CONFIG_BOOTMETH_EXTLINUX is not set -- cgit v1.1