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-rw-r--r--drivers/cpu/Kconfig2
-rw-r--r--drivers/ddr/fsl/options.c4
-rw-r--r--drivers/mmc/fsl_esdhc.c2
-rw-r--r--drivers/mmc/fsl_esdhc_spl.c67
-rw-r--r--drivers/mmc/mmc.c2
-rw-r--r--drivers/mtd/nand/raw/Kconfig4
-rw-r--r--drivers/mtd/nand/raw/fsl_elbc_nand.c99
-rw-r--r--drivers/mtd/nand/raw/nand_base.c6
-rw-r--r--drivers/pci/pcie_fsl.c2
9 files changed, 141 insertions, 47 deletions
diff --git a/drivers/cpu/Kconfig b/drivers/cpu/Kconfig
index 3d5729f..7897281 100644
--- a/drivers/cpu/Kconfig
+++ b/drivers/cpu/Kconfig
@@ -9,7 +9,7 @@ config CPU
config CPU_MPC83XX
bool "Enable MPC83xx CPU driver"
- depends on CPU
+ depends on CPU && MPC83xx
select CLK_MPC83XX
help
Support CPU cores for SoCs of the MPC83xx series.
diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c
index c000a45..9555b9a 100644
--- a/drivers/ddr/fsl/options.c
+++ b/drivers/ddr/fsl/options.c
@@ -761,7 +761,9 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
* Extract hwconfig from environment since we have not properly setup
* the environment but need it for ddr config params
*/
+#if CONFIG_IS_ENABLED(ENV_SUPPORT)
if (env_get_f("hwconfig", buf, sizeof(buf)) < 0)
+#endif
buf[0] = '\0';
#if defined(CONFIG_SYS_FSL_DDR3) || \
@@ -1408,7 +1410,9 @@ int fsl_use_spd(void)
* Extract hwconfig from environment since we have not properly setup
* the environment but need it for ddr config params
*/
+#if CONFIG_IS_ENABLED(ENV_SUPPORT)
if (env_get_f("hwconfig", buf, sizeof(buf)) < 0)
+#endif
buf[0] = '\0';
/* if hwconfig is not enabled, or "sdram" is not defined, use spd */
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 05a6d0c..fdf2cc2 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -724,7 +724,7 @@ static void esdhc_enable_cache_snooping(struct fsl_esdhc *regs)
setbits_be32(&sysconf->sdhccr, 0x02000000);
#else
- esdhc_write32(&regs->esdhcctl, 0x00000040);
+ esdhc_write32(&regs->esdhcctl, ESDHCCTL_SNOOP);
#endif
}
diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c
index bee7657..ea8f4cd6 100644
--- a/drivers/mmc/fsl_esdhc_spl.c
+++ b/drivers/mmc/fsl_esdhc_spl.c
@@ -14,11 +14,12 @@
* on SDCard, so we must read the MBR to get the start address and code
* length of the u-boot image, then calculate the address of the env.
*/
+#define ESDHC_BOOT_SIGNATURE_OFF 0x40
+#define ESDHC_BOOT_SIGNATURE 0x424f4f54
#define ESDHC_BOOT_IMAGE_SIZE 0x48
#define ESDHC_BOOT_IMAGE_ADDR 0x50
#define MBRDBR_BOOT_SIG_55 0x1fe
#define MBRDBR_BOOT_SIG_AA 0x1ff
-#define CONFIG_CFG_DATA_SECTOR 0
void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst)
@@ -60,8 +61,13 @@ void __noreturn mmc_boot(void)
#ifndef CONFIG_FSL_CORENET
uchar *tmp_buf;
u32 blklen;
+ u32 blk_off;
uchar val;
+#ifndef CONFIG_SPL_FSL_PBL
+ u32 val32;
+#endif
uint i, byte_num;
+ u32 sector;
#endif
u32 offset, code_len;
struct mmc *mmc;
@@ -72,58 +78,83 @@ void __noreturn mmc_boot(void)
hang();
}
+ if (mmc_init(mmc)) {
+ puts("spl: mmc device init failed!\n");
+ hang();
+ }
+
#ifdef CONFIG_FSL_CORENET
offset = CONFIG_SYS_MMC_U_BOOT_OFFS;
- code_len = CONFIG_SYS_MMC_U_BOOT_SIZE;
#else
blklen = mmc->read_bl_len;
+ if (blklen < 512)
+ blklen = 512;
tmp_buf = malloc(blklen);
if (!tmp_buf) {
puts("spl: malloc memory failed!!\n");
hang();
}
+
+ sector = 0;
+again:
memset(tmp_buf, 0, blklen);
/*
* Read source addr from sd card
*/
- err = mmc->block_dev.block_read(&mmc->block_dev,
- CONFIG_CFG_DATA_SECTOR, 1, tmp_buf);
+ blk_start = (sector * 512) / mmc->read_bl_len;
+ blk_off = (sector * 512) % mmc->read_bl_len;
+ blk_cnt = DIV_ROUND_UP(512, mmc->read_bl_len);
+ err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt, tmp_buf);
if (err != 1) {
puts("spl: mmc read failed!!\n");
hang();
}
- val = *(tmp_buf + MBRDBR_BOOT_SIG_55);
+#ifdef CONFIG_SPL_FSL_PBL
+ val = *(tmp_buf + blk_off + MBRDBR_BOOT_SIG_55);
if (0x55 != val) {
- puts("spl: mmc signature is not valid!!\n");
+ puts("spl: mmc MBR/DBR signature is not valid!!\n");
hang();
}
- val = *(tmp_buf + MBRDBR_BOOT_SIG_AA);
+ val = *(tmp_buf + blk_off + MBRDBR_BOOT_SIG_AA);
if (0xAA != val) {
- puts("spl: mmc signature is not valid!!\n");
+ puts("spl: mmc MBR/DBR signature is not valid!!\n");
hang();
}
+#else
+ /*
+ * Booting from On-Chip ROM (eSDHC or eSPI), Document Number: AN3659, Rev. 2, 06/2012.
+ * Pre-PBL BootROMs (MPC8536E, MPC8569E, P2020, P1011, P1012, P1013, P1020, P1021, P1022)
+ * require custom BOOT signature on sector 0 and MBR/DBR signature is not required at all.
+ */
+ byte_num = 4;
+ val32 = 0;
+ for (i = 0; i < byte_num; i++) {
+ val = *(tmp_buf + blk_off + ESDHC_BOOT_SIGNATURE_OFF + i);
+ val32 = (val32 << 8) + val;
+ }
+ if (val32 != ESDHC_BOOT_SIGNATURE) {
+ /* BOOT signature may be on the first 24 sectors (each being 512 bytes) */
+ if (++sector < 24)
+ goto again;
+ puts("spl: mmc BOOT signature is not valid!!\n");
+ hang();
+ }
+#endif
byte_num = 4;
offset = 0;
for (i = 0; i < byte_num; i++) {
- val = *(tmp_buf + ESDHC_BOOT_IMAGE_ADDR + i);
+ val = *(tmp_buf + blk_off + ESDHC_BOOT_IMAGE_ADDR + i);
offset = (offset << 8) + val;
}
offset += CONFIG_SYS_MMC_U_BOOT_OFFS;
- /* Get the code size from offset 0x48 */
- byte_num = 4;
- code_len = 0;
- for (i = 0; i < byte_num; i++) {
- val = *(tmp_buf + ESDHC_BOOT_IMAGE_SIZE + i);
- code_len = (code_len << 8) + val;
- }
- code_len -= CONFIG_SYS_MMC_U_BOOT_OFFS;
+#endif
/*
* Load U-Boot image from mmc into RAM
*/
-#endif
+ code_len = CONFIG_SYS_MMC_U_BOOT_SIZE;
blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len;
err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt,
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index f6ccd83..8a7d073 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -132,7 +132,7 @@ void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
}
#endif
-#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
+#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG) || CONFIG_VAL(LOGLEVEL) >= LOGL_DEBUG
const char *mmc_mode_name(enum bus_mode mode)
{
static const char *const names[] = {
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 1eab21e..d75f371 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -158,6 +158,10 @@ config NAND_FSL_ELBC
help
Enable the Freescale Enhanced Local Bus Controller FCM NAND driver.
+config NAND_FSL_ELBC_DT
+ bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver (DT mode)"
+ depends on NAND_FSL_ELBC
+
config NAND_FSL_IFC
bool "Support Freescale Integrated Flash Controller NAND driver"
select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT
diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c
index ddfd75d..e734139 100644
--- a/drivers/mtd/nand/raw/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c
@@ -20,6 +20,10 @@
#include <asm/io.h>
#include <linux/errno.h>
+#ifdef CONFIG_NAND_FSL_ELBC_DT
+#include <dm/read.h>
+#endif
+
#ifdef VERBOSE_DEBUG
#define DEBUG_ELBC
#define vdbg(format, arg...) printf("DEBUG: " format, ##arg)
@@ -312,6 +316,14 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
fsl_elbc_run_command(mtd);
return;
+ /* RNDOUT moves the pointer inside the page */
+ case NAND_CMD_RNDOUT:
+ vdbg("fsl_elbc_cmdfunc: NAND_CMD_RNDOUT, column: 0x%x.\n",
+ column);
+
+ ctrl->index = column;
+ return;
+
/* READOOB reads only the OOB because no ECC is performed. */
case NAND_CMD_READOOB:
vdbg("fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
@@ -656,7 +668,7 @@ static void fsl_elbc_ctrl_init(void)
elbc_ctrl->addr = NULL;
}
-static int fsl_elbc_chip_init(int devnum, u8 *addr)
+static int fsl_elbc_chip_init(int devnum, u8 *addr, ofnode flash_node)
{
struct mtd_info *mtd;
struct nand_chip *nand;
@@ -704,6 +716,8 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr)
elbc_ctrl->chips[priv->bank] = priv;
/* fill in nand_chip structure */
+ nand->flash_node = flash_node;
+
/* set up function call table */
nand->read_byte = fsl_elbc_read_byte;
nand->write_buf = fsl_elbc_write_buf;
@@ -723,36 +737,39 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr)
nand->controller = &elbc_ctrl->controller;
nand_set_controller_data(nand, priv);
- nand->ecc.read_page = fsl_elbc_read_page;
- nand->ecc.write_page = fsl_elbc_write_page;
- nand->ecc.write_subpage = fsl_elbc_write_subpage;
-
priv->fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT);
- /* If CS Base Register selects full hardware ECC then use it */
- if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
- nand->ecc.mode = NAND_ECC_HW;
-
- nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
- &fsl_elbc_oob_sp_eccm1 :
- &fsl_elbc_oob_sp_eccm0;
+ ret = nand_scan_ident(mtd, 1, NULL);
+ if (ret)
+ return ret;
- nand->ecc.size = 512;
- nand->ecc.bytes = 3;
- nand->ecc.steps = 1;
- nand->ecc.strength = 1;
- } else {
- /* otherwise fall back to software ECC */
+ /* If nand_scan_ident() has not selected ecc.mode, do it now */
+ if (nand->ecc.mode == NAND_ECC_NONE) {
+ /* If CS Base Register selects full hardware ECC then use it */
+ if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
+ &fsl_elbc_oob_sp_eccm1 :
+ &fsl_elbc_oob_sp_eccm0;
+ nand->ecc.size = 512;
+ nand->ecc.bytes = 3;
+ nand->ecc.steps = 1;
+ nand->ecc.strength = 1;
+ } else {
+ /* otherwise fall back to software ECC */
#if defined(CONFIG_NAND_ECC_BCH)
- nand->ecc.mode = NAND_ECC_SOFT_BCH;
+ nand->ecc.mode = NAND_ECC_SOFT_BCH;
#else
- nand->ecc.mode = NAND_ECC_SOFT;
+ nand->ecc.mode = NAND_ECC_SOFT;
#endif
+ }
}
- ret = nand_scan_ident(mtd, 1, NULL);
- if (ret)
- return ret;
+ if (nand->ecc.mode == NAND_ECC_HW) {
+ nand->ecc.read_page = fsl_elbc_read_page;
+ nand->ecc.write_page = fsl_elbc_write_page;
+ nand->ecc.write_subpage = fsl_elbc_write_subpage;
+ }
/* Large-page-specific setup */
if (mtd->writesize == 2048) {
@@ -771,7 +788,7 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr)
priv->fmr |= FMR_ECCM;
/* adjust ecc setup if needed */
- if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
+ if (nand->ecc.mode == NAND_ECC_HW) {
nand->ecc.steps = 4;
nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
&fsl_elbc_oob_lp_eccm1 :
@@ -796,6 +813,8 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr)
return 0;
}
+#ifndef CONFIG_NAND_FSL_ELBC_DT
+
#ifndef CONFIG_SYS_NAND_BASE_LIST
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#endif
@@ -808,5 +827,35 @@ void board_nand_init(void)
int i;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- fsl_elbc_chip_init(i, (u8 *)base_address[i]);
+ fsl_elbc_chip_init(i, (u8 *)base_address[i], ofnode_null());
+}
+
+#else
+
+static int fsl_elbc_nand_probe(struct udevice *dev)
+{
+ return fsl_elbc_chip_init(0, (void *)dev_read_addr(dev), dev_ofnode(dev));
}
+
+static const struct udevice_id fsl_elbc_nand_dt_ids[] = {
+ { .compatible = "fsl,elbc-fcm-nand", },
+ {}
+};
+
+U_BOOT_DRIVER(fsl_elbc_nand) = {
+ .name = "fsl_elbc_nand",
+ .id = UCLASS_MTD,
+ .of_match = fsl_elbc_nand_dt_ids,
+ .probe = fsl_elbc_nand_probe,
+};
+
+void board_nand_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MTD, DM_DRIVER_GET(fsl_elbc_nand), &dev);
+ if (ret && ret != -ENODEV)
+ printf("Failed to initialize fsl_elbc_nand NAND controller. (error %d)\n", ret);
+}
+#endif
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index a007603..6f81257 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -4598,6 +4598,12 @@ static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, ofnode nod
ecc_mode = NAND_ECC_SOFT_BCH;
}
+ if (ecc_mode == NAND_ECC_SOFT) {
+ str = ofnode_read_string(node, "nand-ecc-algo");
+ if (str && !strcmp(str, "bch"))
+ ecc_mode = NAND_ECC_SOFT_BCH;
+ }
+
ecc_strength = ofnode_read_s32_default(node,
"nand-ecc-strength", -1);
ecc_step = ofnode_read_s32_default(node,
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index f5ba349..59c38f9 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -646,7 +646,7 @@ static struct fsl_pcie_data t2080_data = {
};
static const struct udevice_id fsl_pcie_ids[] = {
- { .compatible = "fsl,pcie-mpc8548", .data = (ulong)&p1_p2_data },
+ { .compatible = "fsl,mpc8548-pcie", .data = (ulong)&p1_p2_data },
{ .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data },
{ .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data },
{ .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data },
generated by cgit v1.1 at 2024-12-01 18:37:04 +0000