diff options
Diffstat (limited to 'drivers/timer')
| -rw-r--r-- | drivers/timer/Kconfig | 6 | ||||
| -rw-r--r-- | drivers/timer/Makefile | 2 | ||||
| -rw-r--r-- | drivers/timer/ag101p_timer.c | 117 | ||||
| -rw-r--r-- | drivers/timer/atcpit100_timer.c | 112 |
4 files changed, 0 insertions, 237 deletions
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 8fad59b..672746a 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -40,12 +40,6 @@ config TIMER_EARLY use an early timer. These functions must be supported by your timer driver: timer_early_get_count() and timer_early_get_rate(). -config AG101P_TIMER - bool "AG101P timer support" - depends on TIMER && NDS32 - help - Select this to enable a timer for AG01P devices. - config ALTERA_TIMER bool "Altera timer support" depends on TIMER diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index 58da6c1..17f9f1d 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -3,12 +3,10 @@ # Copyright (C) 2015 Thomas Chou <thomas@wytron.com.tw> obj-y += timer-uclass.o -obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o obj-$(CONFIG_ANDES_PLMT_TIMER) += andes_plmt_timer.o obj-$(CONFIG_ARC_TIMER) += arc_timer.o obj-$(CONFIG_AST_TIMER) += ast_timer.o -obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o obj-$(CONFIG_ATMEL_PIT_TIMER) += atmel_pit_timer.o obj-$(CONFIG_ATMEL_TCB_TIMER) += atmel_tcb_timer.o obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o diff --git a/drivers/timer/ag101p_timer.c b/drivers/timer/ag101p_timer.c deleted file mode 100644 index 27cf9b0..0000000 --- a/drivers/timer/ag101p_timer.c +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Andestech ATFTMR010 timer driver - * - * (C) Copyright 2016 - * Rick Chen, NDS32 Software Engineering, rick@andestech.com - */ -#include <common.h> -#include <dm.h> -#include <errno.h> -#include <timer.h> -#include <linux/io.h> - -/* - * Timer Control Register - */ -#define T3_UPDOWN (1 << 11) -#define T2_UPDOWN (1 << 10) -#define T1_UPDOWN (1 << 9) -#define T3_OFENABLE (1 << 8) -#define T3_CLOCK (1 << 7) -#define T3_ENABLE (1 << 6) -#define T2_OFENABLE (1 << 5) -#define T2_CLOCK (1 << 4) -#define T2_ENABLE (1 << 3) -#define T1_OFENABLE (1 << 2) -#define T1_CLOCK (1 << 1) -#define T1_ENABLE (1 << 0) - -/* - * Timer Interrupt State & Mask Registers - */ -#define T3_OVERFLOW (1 << 8) -#define T3_MATCH2 (1 << 7) -#define T3_MATCH1 (1 << 6) -#define T2_OVERFLOW (1 << 5) -#define T2_MATCH2 (1 << 4) -#define T2_MATCH1 (1 << 3) -#define T1_OVERFLOW (1 << 2) -#define T1_MATCH2 (1 << 1) -#define T1_MATCH1 (1 << 0) - -struct atftmr_timer_regs { - u32 t1_counter; /* 0x00 */ - u32 t1_load; /* 0x04 */ - u32 t1_match1; /* 0x08 */ - u32 t1_match2; /* 0x0c */ - u32 t2_counter; /* 0x10 */ - u32 t2_load; /* 0x14 */ - u32 t2_match1; /* 0x18 */ - u32 t2_match2; /* 0x1c */ - u32 t3_counter; /* 0x20 */ - u32 t3_load; /* 0x24 */ - u32 t3_match1; /* 0x28 */ - u32 t3_match2; /* 0x2c */ - u32 cr; /* 0x30 */ - u32 int_state; /* 0x34 */ - u32 int_mask; /* 0x38 */ -}; - -struct atftmr_timer_plat { - struct atftmr_timer_regs *regs; -}; - -static u64 atftmr_timer_get_count(struct udevice *dev) -{ - struct atftmr_timer_plat *plat = dev_get_plat(dev); - struct atftmr_timer_regs *const regs = plat->regs; - u32 val; - val = readl(®s->t3_counter); - return timer_conv_64(val); -} - -static int atftmr_timer_probe(struct udevice *dev) -{ - struct atftmr_timer_plat *plat = dev_get_plat(dev); - struct atftmr_timer_regs *const regs = plat->regs; - u32 cr; - writel(0, ®s->t3_load); - writel(0, ®s->t3_counter); - writel(TIMER_LOAD_VAL, ®s->t3_match1); - writel(TIMER_LOAD_VAL, ®s->t3_match2); - /* disable interrupts */ - writel(T3_MATCH1|T3_MATCH2|T3_OVERFLOW , ®s->int_mask); - cr = readl(®s->cr); - cr |= (T3_ENABLE|T3_UPDOWN); - writel(cr, ®s->cr); - return 0; -} - -static int atftme_timer_of_to_plat(struct udevice *dev) -{ - struct atftmr_timer_plat *plat = dev_get_plat(dev); - plat->regs = map_physmem(dev_read_addr(dev), - sizeof(struct atftmr_timer_regs), - MAP_NOCACHE); - return 0; -} - -static const struct timer_ops ag101p_timer_ops = { - .get_count = atftmr_timer_get_count, -}; - -static const struct udevice_id ag101p_timer_ids[] = { - { .compatible = "andestech,attmr010" }, - {} -}; - -U_BOOT_DRIVER(altera_timer) = { - .name = "ag101p_timer", - .id = UCLASS_TIMER, - .of_match = ag101p_timer_ids, - .of_to_plat = atftme_timer_of_to_plat, - .plat_auto = sizeof(struct atftmr_timer_plat), - .probe = atftmr_timer_probe, - .ops = &ag101p_timer_ops, -}; diff --git a/drivers/timer/atcpit100_timer.c b/drivers/timer/atcpit100_timer.c deleted file mode 100644 index fbc7fac..0000000 --- a/drivers/timer/atcpit100_timer.c +++ /dev/null @@ -1,112 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Andestech ATCPIT100 timer driver - * - * (C) Copyright 2016 - * Rick Chen, NDS32 Software Engineering, rick@andestech.com - */ -#include <common.h> -#include <dm.h> -#include <errno.h> -#include <timer.h> -#include <linux/io.h> - -#define REG32_TMR(x) (*(u32 *) ((plat->regs) + (x>>2))) - -/* - * Definition of register offsets - */ - -/* ID and Revision Register */ -#define ID_REV 0x0 - -/* Configuration Register */ -#define CFG 0x10 - -/* Interrupt Enable Register */ -#define INT_EN 0x14 -#define CH_INT_EN(c , i) ((1<<i)<<(4*c)) - -/* Interrupt Status Register */ -#define INT_STA 0x18 -#define CH_INT_STA(c , i) ((1<<i)<<(4*c)) - -/* Channel Enable Register */ -#define CH_EN 0x1C -#define CH_TMR_EN(c , t) ((1<<t)<<(4*c)) - -/* Ch n Control REgister */ -#define CH_CTL(n) (0x20+0x10*n) -/* Channel clock source , bit 3 , 0:External clock , 1:APB clock */ -#define APB_CLK (1<<3) -/* Channel mode , bit 0~2 */ -#define TMR_32 1 -#define TMR_16 2 -#define TMR_8 3 -#define PWM 4 - -#define CH_REL(n) (0x24+0x10*n) -#define CH_CNT(n) (0x28+0x10*n) - -struct atctmr_timer_regs { - u32 id_rev; /* 0x00 */ - u32 reservd[3]; /* 0x04 ~ 0x0c */ - u32 cfg; /* 0x10 */ - u32 int_en; /* 0x14 */ - u32 int_st; /* 0x18 */ - u32 ch_en; /* 0x1c */ - u32 ch0_ctrl; /* 0x20 */ - u32 ch0_reload; /* 0x24 */ - u32 ch0_cntr; /* 0x28 */ - u32 reservd1; /* 0x2c */ - u32 ch1_ctrl; /* 0x30 */ - u32 ch1_reload; /* 0x34 */ - u32 int_mask; /* 0x38 */ -}; - -struct atcpit_timer_plat { - u32 *regs; -}; - -static u64 atcpit_timer_get_count(struct udevice *dev) -{ - struct atcpit_timer_plat *plat = dev_get_plat(dev); - u32 val; - val = ~(REG32_TMR(CH_CNT(1))+0xffffffff); - return timer_conv_64(val); -} - -static int atcpit_timer_probe(struct udevice *dev) -{ - struct atcpit_timer_plat *plat = dev_get_plat(dev); - REG32_TMR(CH_REL(1)) = 0xffffffff; - REG32_TMR(CH_CTL(1)) = APB_CLK|TMR_32; - REG32_TMR(CH_EN) |= CH_TMR_EN(1 , 0); - return 0; -} - -static int atcpit_timer_of_to_plat(struct udevice *dev) -{ - struct atcpit_timer_plat *plat = dev_get_plat(dev); - plat->regs = map_physmem(dev_read_addr(dev), 0x100 , MAP_NOCACHE); - return 0; -} - -static const struct timer_ops atcpit_timer_ops = { - .get_count = atcpit_timer_get_count, -}; - -static const struct udevice_id atcpit_timer_ids[] = { - { .compatible = "andestech,atcpit100" }, - {} -}; - -U_BOOT_DRIVER(atcpit100_timer) = { - .name = "atcpit100_timer", - .id = UCLASS_TIMER, - .of_match = atcpit_timer_ids, - .of_to_plat = atcpit_timer_of_to_plat, - .plat_auto = sizeof(struct atcpit_timer_plat), - .probe = atcpit_timer_probe, - .ops = &atcpit_timer_ops, -}; |