diff options
Diffstat (limited to 'drivers/timer/ag101p_timer.c')
| -rw-r--r-- | drivers/timer/ag101p_timer.c | 117 |
1 files changed, 0 insertions, 117 deletions
diff --git a/drivers/timer/ag101p_timer.c b/drivers/timer/ag101p_timer.c deleted file mode 100644 index 27cf9b0..0000000 --- a/drivers/timer/ag101p_timer.c +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Andestech ATFTMR010 timer driver - * - * (C) Copyright 2016 - * Rick Chen, NDS32 Software Engineering, rick@andestech.com - */ -#include <common.h> -#include <dm.h> -#include <errno.h> -#include <timer.h> -#include <linux/io.h> - -/* - * Timer Control Register - */ -#define T3_UPDOWN (1 << 11) -#define T2_UPDOWN (1 << 10) -#define T1_UPDOWN (1 << 9) -#define T3_OFENABLE (1 << 8) -#define T3_CLOCK (1 << 7) -#define T3_ENABLE (1 << 6) -#define T2_OFENABLE (1 << 5) -#define T2_CLOCK (1 << 4) -#define T2_ENABLE (1 << 3) -#define T1_OFENABLE (1 << 2) -#define T1_CLOCK (1 << 1) -#define T1_ENABLE (1 << 0) - -/* - * Timer Interrupt State & Mask Registers - */ -#define T3_OVERFLOW (1 << 8) -#define T3_MATCH2 (1 << 7) -#define T3_MATCH1 (1 << 6) -#define T2_OVERFLOW (1 << 5) -#define T2_MATCH2 (1 << 4) -#define T2_MATCH1 (1 << 3) -#define T1_OVERFLOW (1 << 2) -#define T1_MATCH2 (1 << 1) -#define T1_MATCH1 (1 << 0) - -struct atftmr_timer_regs { - u32 t1_counter; /* 0x00 */ - u32 t1_load; /* 0x04 */ - u32 t1_match1; /* 0x08 */ - u32 t1_match2; /* 0x0c */ - u32 t2_counter; /* 0x10 */ - u32 t2_load; /* 0x14 */ - u32 t2_match1; /* 0x18 */ - u32 t2_match2; /* 0x1c */ - u32 t3_counter; /* 0x20 */ - u32 t3_load; /* 0x24 */ - u32 t3_match1; /* 0x28 */ - u32 t3_match2; /* 0x2c */ - u32 cr; /* 0x30 */ - u32 int_state; /* 0x34 */ - u32 int_mask; /* 0x38 */ -}; - -struct atftmr_timer_plat { - struct atftmr_timer_regs *regs; -}; - -static u64 atftmr_timer_get_count(struct udevice *dev) -{ - struct atftmr_timer_plat *plat = dev_get_plat(dev); - struct atftmr_timer_regs *const regs = plat->regs; - u32 val; - val = readl(®s->t3_counter); - return timer_conv_64(val); -} - -static int atftmr_timer_probe(struct udevice *dev) -{ - struct atftmr_timer_plat *plat = dev_get_plat(dev); - struct atftmr_timer_regs *const regs = plat->regs; - u32 cr; - writel(0, ®s->t3_load); - writel(0, ®s->t3_counter); - writel(TIMER_LOAD_VAL, ®s->t3_match1); - writel(TIMER_LOAD_VAL, ®s->t3_match2); - /* disable interrupts */ - writel(T3_MATCH1|T3_MATCH2|T3_OVERFLOW , ®s->int_mask); - cr = readl(®s->cr); - cr |= (T3_ENABLE|T3_UPDOWN); - writel(cr, ®s->cr); - return 0; -} - -static int atftme_timer_of_to_plat(struct udevice *dev) -{ - struct atftmr_timer_plat *plat = dev_get_plat(dev); - plat->regs = map_physmem(dev_read_addr(dev), - sizeof(struct atftmr_timer_regs), - MAP_NOCACHE); - return 0; -} - -static const struct timer_ops ag101p_timer_ops = { - .get_count = atftmr_timer_get_count, -}; - -static const struct udevice_id ag101p_timer_ids[] = { - { .compatible = "andestech,attmr010" }, - {} -}; - -U_BOOT_DRIVER(altera_timer) = { - .name = "ag101p_timer", - .id = UCLASS_TIMER, - .of_match = ag101p_timer_ids, - .of_to_plat = atftme_timer_of_to_plat, - .plat_auto = sizeof(struct atftmr_timer_plat), - .probe = atftmr_timer_probe, - .ops = &ag101p_timer_ops, -}; |