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-rw-r--r--drivers/pci/Kconfig13
-rw-r--r--drivers/pci/pci-uclass.c9
-rw-r--r--drivers/pci/pci_gt64120.c74
-rw-r--r--drivers/pci/pci_msc01.c72
4 files changed, 163 insertions, 5 deletions
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 517cf95..c49cb6e 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -54,6 +54,19 @@ config PCI_REGION_MULTI_ENTRY
region type. This helps to add support for SoC's like OcteonTX/TX2
where every peripheral is on the PCI bus.
+config PCI_MAP_SYSTEM_MEMORY
+ bool "Map local system memory from a virtual base address"
+ depends on PCI || DM_PCI
+ depends on MIPS
+ default n
+ help
+ Say Y if base address of system memory is being used as a virtual address
+ instead of a physical address (e.g. on MIPS). The PCI core will then remap
+ the virtual memory base address to a physical address when adding the PCI
+ region of type PCI_REGION_SYS_MEMORY.
+ This should only be required on MIPS where CONFIG_SYS_SDRAM_BASE is still
+ being used as virtual address.
+
config PCI_SRIOV
bool "Enable Single Root I/O Virtualization support for PCI"
depends on PCI || DM_PCI
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index fb12732..ce2eb5d 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -1034,10 +1034,13 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node,
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
if (bd->bi_dram[i].size) {
+ phys_addr_t start = bd->bi_dram[i].start;
+
+ if (IS_ENABLED(CONFIG_PCI_MAP_SYSTEM_MEMORY))
+ start = virt_to_phys((void *)(uintptr_t)bd->bi_dram[i].start);
+
pci_set_region(hose->regions + hose->region_count++,
- bd->bi_dram[i].start,
- bd->bi_dram[i].start,
- bd->bi_dram[i].size,
+ start, start, bd->bi_dram[i].size,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
}
}
diff --git a/drivers/pci/pci_gt64120.c b/drivers/pci/pci_gt64120.c
index 80f11fe..e57fedf 100644
--- a/drivers/pci/pci_gt64120.c
+++ b/drivers/pci/pci_gt64120.c
@@ -8,7 +8,7 @@
* Maciej W. Rozycki <macro@mips.com>
*/
-#include <common.h>
+#include <dm.h>
#include <gt64120.h>
#include <init.h>
#include <log.h>
@@ -114,6 +114,7 @@ static int gt_config_access(struct gt64120_pci_controller *gt,
return 0;
}
+#if !IS_ENABLED(CONFIG_DM_PCI)
static int gt_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
int where, u32 *value)
{
@@ -175,3 +176,74 @@ void gt64120_pci_init(void *regs, unsigned long sys_bus, unsigned long sys_phys,
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
}
+#else
+static int gt64120_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
+ uint where, ulong *val,
+ enum pci_size_t size)
+{
+ struct gt64120_pci_controller *gt = dev_get_priv(dev);
+ u32 data = 0;
+
+ if (gt_config_access(gt, PCI_ACCESS_READ, bdf, where, &data)) {
+ *val = pci_get_ff(size);
+ return 0;
+ }
+
+ *val = pci_conv_32_to_size(data, where, size);
+
+ return 0;
+}
+
+static int gt64120_pci_write_config(struct udevice *dev, pci_dev_t bdf,
+ uint where, ulong val,
+ enum pci_size_t size)
+{
+ struct gt64120_pci_controller *gt = dev_get_priv(dev);
+ u32 data = 0;
+
+ if (size == PCI_SIZE_32) {
+ data = val;
+ } else {
+ u32 old;
+
+ if (gt_config_access(gt, PCI_ACCESS_READ, bdf, where, &old))
+ return 0;
+
+ data = pci_conv_size_to_32(old, val, where, size);
+ }
+
+ gt_config_access(gt, PCI_ACCESS_WRITE, bdf, where, &data);
+
+ return 0;
+}
+
+static int gt64120_pci_probe(struct udevice *dev)
+{
+ struct gt64120_pci_controller *gt = dev_get_priv(dev);
+
+ gt->regs = dev_remap_addr(dev);
+ if (!gt->regs)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct dm_pci_ops gt64120_pci_ops = {
+ .read_config = gt64120_pci_read_config,
+ .write_config = gt64120_pci_write_config,
+};
+
+static const struct udevice_id gt64120_pci_ids[] = {
+ { .compatible = "marvell,pci-gt64120" },
+ { }
+};
+
+U_BOOT_DRIVER(gt64120_pci) = {
+ .name = "gt64120_pci",
+ .id = UCLASS_PCI,
+ .of_match = gt64120_pci_ids,
+ .ops = &gt64120_pci_ops,
+ .probe = gt64120_pci_probe,
+ .priv_auto = sizeof(struct gt64120_pci_controller),
+};
+#endif
diff --git a/drivers/pci/pci_msc01.c b/drivers/pci/pci_msc01.c
index 0483820..c17da47 100644
--- a/drivers/pci/pci_msc01.c
+++ b/drivers/pci/pci_msc01.c
@@ -4,7 +4,7 @@
* Author: Paul Burton <paul.burton@mips.com>
*/
-#include <common.h>
+#include <dm.h>
#include <init.h>
#include <msc01.h>
#include <pci.h>
@@ -62,6 +62,7 @@ static int msc01_config_access(struct msc01_pci_controller *msc01,
return 0;
}
+#if !IS_ENABLED(CONFIG_DM_PCI)
static int msc01_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
int where, u32 *value)
{
@@ -123,3 +124,72 @@ void msc01_pci_init(void *base, unsigned long sys_bus, unsigned long sys_phys,
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
}
+#else
+static int msc01_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
+ uint where, ulong *val, enum pci_size_t size)
+{
+ struct msc01_pci_controller *msc01 = dev_get_priv(dev);
+ u32 data = 0;
+
+ if (msc01_config_access(msc01, PCI_ACCESS_READ, bdf, where, &data)) {
+ *val = pci_get_ff(size);
+ return 0;
+ }
+
+ *val = pci_conv_32_to_size(data, where, size);
+
+ return 0;
+}
+
+static int msc01_pci_write_config(struct udevice *dev, pci_dev_t bdf,
+ uint where, ulong val, enum pci_size_t size)
+{
+ struct msc01_pci_controller *msc01 = dev_get_priv(dev);
+ u32 data = 0;
+
+ if (size == PCI_SIZE_32) {
+ data = val;
+ } else {
+ u32 old;
+
+ if (msc01_config_access(msc01, PCI_ACCESS_READ, bdf, where, &old))
+ return 0;
+
+ data = pci_conv_size_to_32(old, val, where, size);
+ }
+
+ msc01_config_access(msc01, PCI_ACCESS_WRITE, bdf, where, &data);
+
+ return 0;
+}
+
+static int msc01_pci_probe(struct udevice *dev)
+{
+ struct msc01_pci_controller *msc01 = dev_get_priv(dev);
+
+ msc01->base = dev_remap_addr(dev);
+ if (!msc01->base)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct dm_pci_ops msc01_pci_ops = {
+ .read_config = msc01_pci_read_config,
+ .write_config = msc01_pci_write_config,
+};
+
+static const struct udevice_id msc01_pci_ids[] = {
+ { .compatible = "mips,pci-msc01" },
+ { }
+};
+
+U_BOOT_DRIVER(msc01_pci) = {
+ .name = "msc01_pci",
+ .id = UCLASS_PCI,
+ .of_match = msc01_pci_ids,
+ .ops = &msc01_pci_ops,
+ .probe = msc01_pci_probe,
+ .priv_auto = sizeof(struct msc01_pci_controller),
+};
+#endif
generated by cgit v1.1 at 2024-11-29 09:24:10 +0000