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-rw-r--r--arch/sandbox/dts/test.dts4
-rw-r--r--drivers/memory/Kconfig17
-rw-r--r--drivers/memory/Makefile2
-rw-r--r--drivers/memory/memory-sandbox.c18
-rw-r--r--drivers/memory/memory-uclass.c13
-rw-r--r--include/dm/uclass-id.h1
-rw-r--r--test/dm/Makefile1
-rw-r--r--test/dm/memory.c21
8 files changed, 77 insertions, 0 deletions
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 70e27cd..db72c64 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -932,6 +932,10 @@
};
};
+ memory-controller {
+ compatible = "sandbox,memory";
+ };
+
misc-test {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index 7271892..c621f5b 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -4,6 +4,23 @@
menu "Memory Controller drivers"
+config MEMORY
+ bool "Enable Driver Model for Memory Controller drivers"
+ depends on DM
+ help
+ Enable driver model for Memory Controller devices.
+ These devices provide Memory bus interface to various devices like
+ SRAM, Ethernet adapters, FPGAs, etc.
+ For now this uclass has no methods yet.
+
+config SANDBOX_MEMORY
+ bool "Enable Sandbox Memory Controller driver"
+ depends on SANDBOX && MEMORY
+ help
+ This is a driver model based Memory Controller driver for sandbox.
+ Currently it is a stub only, as there are no usable uclass methods
+ yet.
+
config STM32_FMC2_EBI
bool "Support for FMC2 External Bus Interface on STM32MP SoCs"
depends on ARCH_STM32MP
diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
index fec52ef..b27f701 100644
--- a/drivers/memory/Makefile
+++ b/drivers/memory/Makefile
@@ -1,3 +1,5 @@
+obj-$(CONFIG_MEMORY) += memory-uclass.o
+obj-$(CONFIG_SANDBOX_MEMORY) += memory-sandbox.o
obj-$(CONFIG_STM32_FMC2_EBI) += stm32-fmc2-ebi.o
obj-$(CONFIG_TI_AEMIF) += ti-aemif.o
diff --git a/drivers/memory/memory-sandbox.c b/drivers/memory/memory-sandbox.c
new file mode 100644
index 0000000..f2ede50
--- /dev/null
+++ b/drivers/memory/memory-sandbox.c
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2022
+ * Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#include <dm.h>
+
+static const struct udevice_id sandbox_memory_match[] = {
+ { .compatible = "sandbox,memory" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(sandbox_memory) = {
+ .name = "sandbox_memory",
+ .id = UCLASS_MEMORY,
+ .of_match = sandbox_memory_match,
+};
diff --git a/drivers/memory/memory-uclass.c b/drivers/memory/memory-uclass.c
new file mode 100644
index 0000000..d6d37fe
--- /dev/null
+++ b/drivers/memory/memory-uclass.c
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2022
+ * Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#include <dm.h>
+
+UCLASS_DRIVER(memory) = {
+ .name = "memory",
+ .id = UCLASS_MEMORY,
+ .post_bind = dm_scan_fdt_dev,
+};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index c2b1588..4b2c323 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -77,6 +77,7 @@ enum uclass_id {
UCLASS_MASS_STORAGE, /* Mass storage device */
UCLASS_MDIO, /* MDIO bus */
UCLASS_MDIO_MUX, /* MDIO MUX/switch */
+ UCLASS_MEMORY, /* Memory Controller device */
UCLASS_MISC, /* Miscellaneous device */
UCLASS_MMC, /* SD / MMC card or chip */
UCLASS_MOD_EXP, /* RSA Mod Exp device */
diff --git a/test/dm/Makefile b/test/dm/Makefile
index 499e769..fd7d310 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -57,6 +57,7 @@ obj-$(CONFIG_LED) += led.o
obj-$(CONFIG_DM_MAILBOX) += mailbox.o
obj-$(CONFIG_DM_MDIO) += mdio.o
obj-$(CONFIG_DM_MDIO_MUX) += mdio_mux.o
+obj-$(CONFIG_MEMORY) += memory.o
obj-$(CONFIG_MISC) += misc.o
obj-$(CONFIG_DM_MMC) += mmc.o
obj-$(CONFIG_CMD_MUX) += mux-cmd.o
diff --git a/test/dm/memory.c b/test/dm/memory.c
new file mode 100644
index 0000000..7d9500a
--- /dev/null
+++ b/test/dm/memory.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2022
+ * Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#include <dm.h>
+#include <dm/test.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+static int dm_test_memory(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+
+ ut_assertok(uclass_first_device_err(UCLASS_MEMORY, &dev));
+
+ return 0;
+}
+
+DM_TEST(dm_test_memory, UT_TESTF_SCAN_FDT);