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| author | Valentine Barshak <valentine.barshak@cogentembedded.com> | 2019-04-23 23:44:57 +0300 |
|---|---|---|
| committer | Marek Vasut <marek.vasut+renesas@mailbox.org> | 2023-06-08 22:26:52 +0200 |
| commit | ed2f65f0105dacb98e5c4d2b435dd009de06c2d1 (patch) | |
| tree | d5cb497991cdf09e1ebd3407f1b367050c71e1e8 /include/configs | |
| parent | bd13df8b5d6df94beaa4acc61cf4d85b93e53a1a (diff) | |
| download | u-boot-ed2f65f0105dacb98e5c4d2b435dd009de06c2d1.zip u-boot-ed2f65f0105dacb98e5c4d2b435dd009de06c2d1.tar.gz u-boot-ed2f65f0105dacb98e5c4d2b435dd009de06c2d1.tar.bz2 | |
ARM: renesas: Add R8A77980 V3HSK board and CPLD code
Add board code for the R8A77980 V3HSK board.
Add CPLD sysreset driver to the R-Car V3H SK board.
Extracted from a larger patch by Valentine Barshak.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync configs and board code with V3H Condor, squash CPLD driver in]
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/v3hsk.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/include/configs/v3hsk.h b/include/configs/v3hsk.h new file mode 100644 index 0000000..58c2e88 --- /dev/null +++ b/include/configs/v3hsk.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * include/configs/v3hsk.h + * This file is V3HSK board configuration. + * + * Copyright (C) 2019 Renesas Electronics Corporation + * Copyright (C) 2019 Cogent Embedded, Inc. + */ + +#ifndef __V3HSK_H +#define __V3HSK_H + +#include "rcar-gen3-common.h" + +/* Environment compatibility */ + +/* SH Ether */ +#define CFG_SH_ETHER_USE_PORT 0 +#define CFG_SH_ETHER_PHY_ADDR 0x0 +#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID +#define CFG_SH_ETHER_CACHE_WRITEBACK +#define CFG_SH_ETHER_CACHE_INVALIDATE +#define CFG_SH_ETHER_ALIGNE_SIZE 64 + +/* Board Clock */ +/* XTAL_CLK : 33.33MHz */ + +#endif /* __V3HSK_H */ |