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| author | Alex Leibovich <alexl@marvell.com> | 2021-02-19 17:11:11 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2021-02-26 10:22:29 +0100 |
| commit | 5d88723ca4de4c71ad4f18c98241431ff158c479 (patch) | |
| tree | c7dafe010642df13276314968da9fe618ff25c1f /drivers/ddr | |
| parent | ab7dda724f4a646ab68f928570496d2bef032793 (diff) | |
| download | u-boot-5d88723ca4de4c71ad4f18c98241431ff158c479.zip u-boot-5d88723ca4de4c71ad4f18c98241431ff158c479.tar.gz u-boot-5d88723ca4de4c71ad4f18c98241431ff158c479.tar.bz2 | |
ddr: marvell: a38x: add ddr32 support
commit 32800667b375ebd1f82120da0f3479b1cf52d96d upstream.
Required changes made for 32bit ddr support.
An update is made to the topology map, according to
bus_act_mask, set in the dram_port.c
Signed-off-by: Alex Leibovich <alexl@marvell.com>
Reviewed-by: Nadav Haklai <Nadav.Haklai@cavium.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Diffstat (limited to 'drivers/ddr')
| -rw-r--r-- | drivers/ddr/marvell/a38x/mv_ddr_topology.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.c b/drivers/ddr/marvell/a38x/mv_ddr_topology.c index 09840b1..f2cd7c0 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_topology.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.c @@ -144,6 +144,9 @@ unsigned short mv_ddr_bus_bit_mask_get(void) unsigned int octets_per_if_num = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE); if (tm->cfg_src == MV_DDR_CFG_SPD) { + if (tm->bus_act_mask == BUS_MASK_32BIT) + tm->spd_data.byte_fields.byte_13.all_bits = MV_DDR_PRI_BUS_WIDTH_32; + enum mv_ddr_pri_bus_width pri_bus_width = mv_ddr_spd_pri_bus_width_get(&tm->spd_data); enum mv_ddr_bus_width_ext bus_width_ext = mv_ddr_spd_bus_width_ext_get(&tm->spd_data); @@ -151,7 +154,7 @@ unsigned short mv_ddr_bus_bit_mask_get(void) case MV_DDR_PRI_BUS_WIDTH_16: pri_and_ext_bus_width = BUS_MASK_16BIT; break; - case MV_DDR_PRI_BUS_WIDTH_32: + case MV_DDR_PRI_BUS_WIDTH_32: /*each bit represents byte, so 0xf-is means 4 bytes-32 bit*/ pri_and_ext_bus_width = BUS_MASK_32BIT; break; case MV_DDR_PRI_BUS_WIDTH_64: |