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author | Alexey Brodkin <abrodkin@synopsys.com> | 2019-07-18 15:51:25 +0300 |
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committer | Alexey Brodkin <abrodkin@synopsys.com> | 2019-09-03 19:05:34 +0300 |
commit | 9ddaf1d51602a531d463f9047958b9de233123ca (patch) | |
tree | 0a751eeb493bac5d1ae14084406e04e600e76b02 /board/synopsys | |
parent | d22c8be964a870f59d2fdab6c67cefa0c4799364 (diff) | |
download | u-boot-9ddaf1d51602a531d463f9047958b9de233123ca.zip u-boot-9ddaf1d51602a531d463f9047958b9de233123ca.tar.gz u-boot-9ddaf1d51602a531d463f9047958b9de233123ca.tar.bz2 |
arc: emsdp: Add initialization of PSRAM
If the "Page Mode" is not enabled on the device,
read operations from PSRAM may result in incorrect data.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Diffstat (limited to 'board/synopsys')
-rw-r--r-- | board/synopsys/emsdp/emsdp.c | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/board/synopsys/emsdp/emsdp.c b/board/synopsys/emsdp/emsdp.c index c0770b5..7a3fd5b 100644 --- a/board/synopsys/emsdp/emsdp.c +++ b/board/synopsys/emsdp/emsdp.c @@ -48,6 +48,43 @@ int mach_cpu_init(void) return 0; } +int board_early_init_r(void) +{ +#define EMSDP_PSRAM_BASE 0xf2001000 +#define PSRAM_FLASH_CONFIG_REG_0 (void *)(EMSDP_PSRAM_BASE + 0x10) +#define PSRAM_FLASH_CONFIG_REG_1 (void *)(EMSDP_PSRAM_BASE + 0x14) +#define CRE_ENABLE BIT(31) +#define CRE_DRIVE_CMD BIT(6) + +#define PSRAM_RCR_DPD BIT(1) +#define PSRAM_RCR_PAGE_MODE BIT(7) + +/* + * PSRAM_FLASH_CONFIG_REG_x[30:15] to the address lines[16:1] of flash, + * thus "<< 1". + */ +#define PSRAM_RCR_SETUP ((PSRAM_RCR_DPD | PSRAM_RCR_PAGE_MODE) << 1) + + // Switch PSRAM controller to command mode + writel(CRE_ENABLE | CRE_DRIVE_CMD, PSRAM_FLASH_CONFIG_REG_0); + // Program Refresh Configuration Register (RCR) for BANK0 + writew(0, (void *)(0x10000000 + PSRAM_RCR_SETUP)); + // Switch PSRAM controller back to memory mode + writel(0, PSRAM_FLASH_CONFIG_REG_0); + + + // Switch PSRAM controller to command mode + writel(CRE_ENABLE | CRE_DRIVE_CMD, PSRAM_FLASH_CONFIG_REG_1); + // Program Refresh Configuration Register (RCR) for BANK1 + writew(0, (void *)(0x10800000 + PSRAM_RCR_SETUP)); + // Switch PSRAM controller back to memory mode + writel(0, PSRAM_FLASH_CONFIG_REG_1); + + printf("PSRAM initialized.\n"); + + return 0; +} + int board_mmc_init(bd_t *bis) { struct dwmci_host *host = NULL; |