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| author | Tom Rini <trini@konsulko.com> | 2023-07-31 11:31:26 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-07-31 11:33:51 -0400 |
| commit | 4e619e8d4fd68095bc665a78f2651d8e478a4534 (patch) | |
| tree | 6f3e733f5dd68f25187f55bddb8575c30405450b /arch/arm/dts/rk356x.dtsi | |
| parent | 6aab91a8daf298e22f1dcf7937bc3dd09a29bb08 (diff) | |
| parent | 1f54f71b182e3515f72870a75ce2ba769b00b1f3 (diff) | |
| download | u-boot-WIP/31Jul2023.zip u-boot-WIP/31Jul2023.tar.gz u-boot-WIP/31Jul2023.tar.bz2 | |
Merge tag 'u-boot-rockchip-20230731' of https://source.denx.de/u-boot/custodians/u-boot-rockchipWIP/31Jul2023
- Update dwc3 generic driver and update support for rk3568/rk3328;
- Add boards:
rk3566: Pine64 Quartz64-A/B, SOQuartz on Model A/Blade/CM4-IO
rk3568: Radxa E25 Carrier Board
rk3588: Radxa ROCK5A
- Fixes and updates for chromebook veryon/jerry/speedy;
- SPI support fixes for rk3399/rk3568/rk3588;
- rk3588 usbdp phy support;
- dts and config updates for different boards;
Diffstat (limited to 'arch/arm/dts/rk356x.dtsi')
| -rw-r--r-- | arch/arm/dts/rk356x.dtsi | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/arch/arm/dts/rk356x.dtsi b/arch/arm/dts/rk356x.dtsi index e0591c1..61680c7 100644 --- a/arch/arm/dts/rk356x.dtsi +++ b/arch/arm/dts/rk356x.dtsi @@ -422,8 +422,9 @@ clock-names = "xin24m"; #clock-cells = <1>; #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; - assigned-clock-rates = <1200000000>, <200000000>; + assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; + assigned-clock-rates = <32768>, <1200000000>, <200000000>; + assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>; rockchip,grf = <&grf>; }; @@ -743,8 +744,8 @@ compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x00 0xfe060000 0x00 0x10000>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "pclk", "hclk"; - clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>; + clock-names = "pclk"; + clocks = <&cru PCLK_DSITX_0>; phy-names = "dphy"; phys = <&dsi_dphy0>; power-domains = <&power RK3568_PD_VO>; @@ -771,8 +772,8 @@ compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x0 0xfe070000 0x0 0x10000>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "pclk", "hclk"; - clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>; + clock-names = "pclk"; + clocks = <&cru PCLK_DSITX_1>; phy-names = "dphy"; phys = <&dsi_dphy1>; power-domains = <&power RK3568_PD_VO>; @@ -966,6 +967,7 @@ clock-names = "aclk_mst", "aclk_slv", "aclk_dbi", "pclk", "aux"; device_type = "pci"; + #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie_intc 0>, <0 0 0 2 &pcie_intc 1>, |