global: Remove unused CONFIG definesWIP/migrate-some-unobvious-CONFIG-syms

Remove some CONFIG symbols and related comments, etc, that are unused
within the code itself at this point.

Signed-off-by: Tom Rini <trini@konsulko.com>

9 files changed, 3 insertions, 73 deletions

diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
index 3090393..24f3b4e 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200.h
@@ -126,6 +126,4 @@
 #define ATMEL_PIO_PORTS		4	/* theese SoCs have 4 PIO */
 #define ATMEL_PMC_UHP		AT91RM9200_PMC_UHP
 
-#define CONFIG_SYS_ATMEL_CPU_NAME	"AT91RM9200"
-
 #endif
diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h
index dab8b26..0c23744 100644
--- a/arch/m68k/include/asm/immap.h
+++ b/arch/m68k/include/asm/immap.h
@@ -13,7 +13,6 @@
 #include <asm/immap_520x.h>
 #include <asm/m520x.h>
 
-#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
 #define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
 
 /* Timer */
@@ -36,7 +35,6 @@
 #include <asm/immap_5235.h>
 #include <asm/m5235.h>
 
-#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
 #define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 /* Timer */
@@ -104,7 +102,6 @@
 #include <asm/immap_5271.h>
 #include <asm/m5271.h>
 
-#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
 #define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 /* Timer */
@@ -127,7 +124,6 @@
 #include <asm/immap_5272.h>
 #include <asm/m5272.h>
 
-#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
 #define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC)
@@ -150,8 +146,6 @@
 #include <asm/immap_5275.h>
 #include <asm/m5275.h>
 
-#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
-#define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
 #define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
@@ -174,7 +168,6 @@
 #include <asm/immap_5282.h>
 #include <asm/m5282.h>
 
-#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
 #define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
@@ -221,8 +214,6 @@
 #include <asm/immap_5301x.h>
 #include <asm/m5301x.h>
 
-#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
-#define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
 #define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
 
 /* Timer */
@@ -245,7 +236,6 @@
 #include <asm/immap_5329.h>
 #include <asm/m5329.h>
 
-#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
 #define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
 
 /* Timer */
@@ -268,9 +258,6 @@
 #include <asm/immap_5441x.h>
 #include <asm/m5441x.h>
 
-#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
-#define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
-
 #if (CFG_SYS_UART_PORT < 4)
 #define CONFIG_SYS_UART_BASE		(MMAP_UART0 + \
 					(CFG_SYS_UART_PORT * 0x4000))
@@ -303,9 +290,6 @@
 #include <asm/m547x_8x.h>
 
 #ifdef CONFIG_FSLDMAFEC
-#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
-#define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
-
 #define FEC0_RX_TASK		0
 #define FEC0_TX_TASK		1
 #define FEC0_RX_PRIORITY	6
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 19e63eb..f7e1a80 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -980,37 +980,6 @@
 #define PVR_5200B	0x80822014
 
 /*
- * 405EX/EXr CHIP_21 Errata
- */
-#ifdef CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
-#define CONFIG_SYS_4xx_CHIP_21_ERRATA
-#define CONFIG_405EX_CHIP21_PVR_REV_C	PVR_405EX1_RC
-#define CONFIG_405EX_CHIP21_PVR_REV_D	PVR_405EX1_RD
-#define CONFIG_405EX_CHIP21_ECID3_REV_D	0x0
-#endif
-
-#ifdef CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY
-#define CONFIG_SYS_4xx_CHIP_21_ERRATA
-#define CONFIG_405EX_CHIP21_PVR_REV_C	PVR_405EX2_RC
-#define CONFIG_405EX_CHIP21_PVR_REV_D	PVR_405EX2_RD
-#define CONFIG_405EX_CHIP21_ECID3_REV_D	0x1
-#endif
-
-#ifdef CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY
-#define CONFIG_SYS_4xx_CHIP_21_ERRATA
-#define CONFIG_405EX_CHIP21_PVR_REV_C	PVR_405EXR1_RC
-#define CONFIG_405EX_CHIP21_PVR_REV_D	PVR_405EXR1_RD
-#define CONFIG_405EX_CHIP21_ECID3_REV_D	0x2
-#endif
-
-#ifdef CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY
-#define CONFIG_SYS_4xx_CHIP_21_ERRATA
-#define CONFIG_405EX_CHIP21_PVR_REV_C	PVR_405EXR2_RC
-#define CONFIG_405EX_CHIP21_PVR_REV_D	PVR_405EXR2_RD
-#define CONFIG_405EX_CHIP21_ECID3_REV_D	0x3
-#endif
-
-/*
  * System Version Register
  */
 
diff --git a/doc/README.socfpga b/doc/README.socfpga
index 4d73398..e5adb62 100644
--- a/doc/README.socfpga
+++ b/doc/README.socfpga
@@ -6,16 +6,6 @@ This README is about U-Boot and SPL support for Altera's ARM Cortex-A9MPCore
 based SOCFPGA. To know more about the hardware itself, please refer to
 www.altera.com.
 
-
-socfpga_dw_mmc
---------------
-
-Here are macro and detailed configuration required to enable DesignWare SDMMC
-controller support within SOCFPGA
-
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT	256
--> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM
-
 ---------------------------------------------------------------------
 Cyclone 5 / Arria 5 generating the handoff header files for U-Boot SPL
 ---------------------------------------------------------------------
diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c
index a042450..0a1fe56 100644
--- a/drivers/net/eepro100.c
+++ b/drivers/net/eepro100.c
@@ -168,9 +168,7 @@ struct descriptor {		/* A generic descriptor. */
 	unsigned char params[0];
 };
 
-#define CONFIG_SYS_CMD_EL		0x8000
 #define CONFIG_SYS_CMD_SUSPEND		0x4000
-#define CONFIG_SYS_CMD_INT		0x2000
 #define CONFIG_SYS_CMD_IAS		0x0001	/* individual address setup */
 #define CONFIG_SYS_CMD_CONFIGURE	0x0002	/* configure */
 
diff --git a/drivers/video/videomodes.c b/drivers/video/videomodes.c
index 69ef736..35955a5 100644
--- a/drivers/video/videomodes.c
+++ b/drivers/video/videomodes.c
@@ -7,8 +7,7 @@
 
 /************************************************************************
   Get Parameters for the video mode:
-  The default video mode can be defined in CONFIG_SYS_DEFAULT_VIDEO_MODE.
-  If undefined, default video mode is set to 0x301
+  The default video mode is set to 0x301
   Parameters can be set via the variable "videomode" in the environment.
   2 diferent ways are possible:
   "videomode=301"   - 301 is a hexadecimal number describing the VESA
diff --git a/drivers/video/videomodes.h b/drivers/video/videomodes.h
index aefe4ef..405f4e1 100644
--- a/drivers/video/videomodes.h
+++ b/drivers/video/videomodes.h
@@ -6,10 +6,6 @@
 
 #include <edid.h>
 
-#ifndef CONFIG_SYS_DEFAULT_VIDEO_MODE
-#define CONFIG_SYS_DEFAULT_VIDEO_MODE	0x301
-#endif
-
 /* Some mode definitions */
 #define FB_SYNC_HOR_HIGH_ACT	1	/* horizontal sync high active	*/
 #define FB_SYNC_VERT_HIGH_ACT	2	/* vertical sync high active	*/
diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h
index 24229f6..f336c6a 100644
--- a/include/fsl_ddr.h
+++ b/include/fsl_ddr.h
@@ -50,13 +50,12 @@ compute_dimm_parameters(const unsigned int ctrl_num,
  *
  * All data structures have to be on the stack
  */
-#define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR
 
 typedef struct {
 	generic_spd_eeprom_t
-	   spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
+	   spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR];
 	struct dimm_params_s
-	   dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
+	   dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR];
 	memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS];
 	common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS];
 	fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS];
diff --git a/include/fsl_usb.h b/include/fsl_usb.h
index c0f076b..a37a6e5 100644
--- a/include/fsl_usb.h
+++ b/include/fsl_usb.h
@@ -43,10 +43,8 @@ struct ccsr_usb_phy {
 #define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0)
 #define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1)
 #define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1)
-#define CONFIG_SYS_FSL_USB_PLLPRG1_PHY_DIV (1 << 0)
 #define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0)
 #define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1)
-#define CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN (1 << 13)
 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
 #define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK (5 << 4)
 #define CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK (6 << 16)
@@ -55,7 +53,6 @@ struct ccsr_usb_phy {
 #define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 << 4)
 #define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
 #define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
-#define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0)
 #define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN (1 << 7)
 #define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK (3 << 4)