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| author | Dinesh Maniyam <dinesh.maniyam@intel.com> | 2023-12-15 15:15:19 +0800 |
|---|---|---|
| committer | Tien Fong Chee <tien.fong.chee@intel.com> | 2024-01-22 16:51:17 +0800 |
| commit | 9d8f814beb7f1857e814a42ec8362323ed88bdcc (patch) | |
| tree | 470ce4a501d7b16c7811df9736d72aecef27044a | |
| parent | 158d648d9f02c9ee0f432bbafeea38aaa55dd943 (diff) | |
| download | u-boot-9d8f814beb7f1857e814a42ec8362323ed88bdcc.zip u-boot-9d8f814beb7f1857e814a42ec8362323ed88bdcc.tar.gz u-boot-9d8f814beb7f1857e814a42ec8362323ed88bdcc.tar.bz2 | |
clk: altera: n5x: Fix MEMCLKMGR_EXTCNTRST_C0CNTRST to bit(0)
MEMCLKMGR_EXTCNTRST_C0CNTRST register defined as BIT[0] in documentation
but it is wrongly defined as BIT[7] in u-boot code. This register is used
to hold associated pingpong counter in reset
while PLL and 5:1 mux configuration is changed.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
| -rw-r--r-- | drivers/clk/altera/clk-mem-n5x.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/altera/clk-mem-n5x.h b/drivers/clk/altera/clk-mem-n5x.h index 7b68701..c6bc44b 100644 --- a/drivers/clk/altera/clk-mem-n5x.h +++ b/drivers/clk/altera/clk-mem-n5x.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ /* - * Copyright (C) 2020-2022 Intel Corporation <www.intel.com> + * Copyright (C) 2020-2023 Intel Corporation <www.intel.com> */ #ifndef _CLK_MEM_N5X_ @@ -77,7 +77,7 @@ #define MEMCLKMGR_PLLOUTDIV_C0CNT_MASK GENMASK(4, 0) #define MEMCLKMGR_PLLOUTDIV_C0CNT_OFFSET 0 -#define MEMCLKMGR_EXTCNTRST_C0CNTRST BIT(7) +#define MEMCLKMGR_EXTCNTRST_C0CNTRST BIT(0) #define MEMCLKMGR_EXTCNTRST_ALLCNTRST \ (MEMCLKMGR_EXTCNTRST_C0CNTRST) |