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| author | Michael Walle <michael@walle.cc> | 2022-05-30 23:02:07 +0200 |
|---|---|---|
| committer | Peng Fan <peng.fan@nxp.com> | 2022-06-20 15:52:45 +0800 |
| commit | 6bdda4b2003fadbcbcc28a1d395ec1f6f6557539 (patch) | |
| tree | 4fd174441b93ae79f561109b68f714bfa7d6227d | |
| parent | 2a9cf320afb051f40a4bbb98aa9a6b1a94332d27 (diff) | |
| download | u-boot-6bdda4b2003fadbcbcc28a1d395ec1f6f6557539.zip u-boot-6bdda4b2003fadbcbcc28a1d395ec1f6f6557539.tar.gz u-boot-6bdda4b2003fadbcbcc28a1d395ec1f6f6557539.tar.bz2 | |
board: sl28: set CPO value
With a 8GiB memory board, it seems that the "very unlikely event" of a
DDR initialization with non-optimal values are not really that unlikely.
It happens in about every other reboot. As described in erratum
A-009942, preset the DEBUG_28 register with an optimal value. The value
iself depends on the memory configuration of the board, but the used
value seems to work well for all variants.
Signed-off-by: Michael Walle <michael@walle.cc>
| -rw-r--r-- | board/kontron/sl28/ddr.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/board/kontron/sl28/ddr.c b/board/kontron/sl28/ddr.c index 4142699..d75b23e 100644 --- a/board/kontron/sl28/ddr.c +++ b/board/kontron/sl28/ddr.c @@ -54,6 +54,9 @@ static fsl_ddr_cfg_regs_t __maybe_unused ddr_cfg_regs = { .ddr_cdr1 = 0x80040000, .ddr_cdr2 = 0x0000bc01, + + /* Erratum A-009942, set optimal CPO value */ + .debug[28] = 0x00700040, }; int fsl_initdram(void) |