ARM: renesas: Add R8A77980 V3HSK board and CPLD code

Add board code for the R8A77980 V3HSK board.
Add CPLD sysreset driver to the R-Car V3H SK board.
Extracted from a larger patch by Valentine Barshak.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync configs and board code with V3H Condor, squash CPLD driver in]

8 files changed, 370 insertions, 0 deletions

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index dd917ae..4b19a93 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1052,6 +1052,7 @@ dtb-$(CONFIG_RCAR_GEN3) += \
 	r8a77970-eagle-u-boot.dtb \
 	r8a77970-v3msk-u-boot.dtb \
 	r8a77980-condor-u-boot.dtb \
+	r8a77980-v3hsk-u-boot.dtb \
 	r8a77990-ebisu-u-boot.dtb \
 	r8a77995-draak-u-boot.dtb
 
diff --git a/arch/arm/dts/r8a77980-v3hsk-u-boot.dts b/arch/arm/dts/r8a77980-v3hsk-u-boot.dts
new file mode 100644
index 0000000..d083df6
--- /dev/null
+++ b/arch/arm/dts/r8a77980-v3hsk-u-boot.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the Eagle board
+ *
+ * Copyright (C) 2019 Cogent Embedded, Inc.
+ */
+
+#include "r8a77980-v3hsk.dts"
+#include "r8a77980-u-boot.dtsi"
+
+/ {
+	aliases {
+		spi0 = &rpc;
+	};
+};
+
+&rpc {
+	num-cs = <1>;
+	status = "okay";
+	spi-max-frequency = <50000000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	flash0: spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "s25fs512s", "spi-flash", "jedec,spi-nor";
+		spi-max-frequency = <50000000>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+		reg = <0>;
+		status = "okay";
+	};
+};
+
+&i2c0 {
+	cpld {
+		compatible = "renesas,v3hsk-cpld";
+		reg = <0x70>;
+		u-boot,i2c-offset-len = <2>;
+	};
+};
diff --git a/arch/arm/mach-rmobile/Kconfig.rcar3 b/arch/arm/mach-rmobile/Kconfig.rcar3
index 46d2742..ad35d10 100644
--- a/arch/arm/mach-rmobile/Kconfig.rcar3
+++ b/arch/arm/mach-rmobile/Kconfig.rcar3
@@ -99,6 +99,11 @@ config TARGET_CONDOR
 	help
           Support for Renesas R-Car Gen3 Condor platform
 
+config TARGET_V3HSK
+	bool "V3HSK board"
+	help
+          Support for Renesas R-Car Gen3 V3HSK platform
+
 config TARGET_DRAAK
 	bool "Draak board"
 	imply R8A77995
@@ -171,6 +176,7 @@ source "board/renesas/eagle/Kconfig"
 source "board/renesas/ebisu/Kconfig"
 source "board/renesas/salvator-x/Kconfig"
 source "board/renesas/ulcb/Kconfig"
+source "board/renesas/v3hsk/Kconfig"
 source "board/renesas/v3msk/Kconfig"
 source "board/beacon/beacon-rzg2m/Kconfig"
 source "board/hoperun/hihope-rzg2/Kconfig"
diff --git a/board/renesas/v3hsk/Kconfig b/board/renesas/v3hsk/Kconfig
new file mode 100644
index 0000000..531ceb7
--- /dev/null
+++ b/board/renesas/v3hsk/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_V3HSK
+
+config SYS_SOC
+	default "rmobile"
+
+config SYS_BOARD
+	default "v3hsk"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "v3hsk"
+
+endif
diff --git a/board/renesas/v3hsk/Makefile b/board/renesas/v3hsk/Makefile
new file mode 100644
index 0000000..a9d597e
--- /dev/null
+++ b/board/renesas/v3hsk/Makefile
@@ -0,0 +1,15 @@
+#
+# board/renesas/v3hsk/Makefile
+#
+# Copyright (C) 2019 Renesas Electronics Corporation
+# Copyright (C) 2019 Cogent Embedded, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y	:= ../rcar-common/gen3-spl.o
+else
+obj-y	:= ../rcar-common/v3-common.o ../rcar-common/common.o
+obj-$(CONFIG_SYSRESET)	+= cpld.o
+endif
diff --git a/board/renesas/v3hsk/cpld.c b/board/renesas/v3hsk/cpld.c
new file mode 100644
index 0000000..6016f6d
--- /dev/null
+++ b/board/renesas/v3hsk/cpld.c
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * V3HSK board CPLD access support
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation
+ * Copyright (C) 2019 Cogent Embedded, Inc.
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <i2c.h>
+#include <linux/err.h>
+#include <sysreset.h>
+#include <command.h>
+
+#define CPLD_ADDR_PRODUCT_0		0x0000 /* R */
+#define CPLD_ADDR_PRODUCT_1		0x0001 /* R */
+#define CPLD_ADDR_PRODUCT_2		0x0002 /* R */
+#define CPLD_ADDR_PRODUCT_3		0x0003 /* R */
+#define CPLD_ADDR_CPLD_VERSION_D	0x0004 /* R */
+#define CPLD_ADDR_CPLD_VERSION_M	0x0005 /* R */
+#define CPLD_ADDR_CPLD_VERSION_Y_0	0x0006 /* R */
+#define CPLD_ADDR_CPLD_VERSION_Y_1	0x0007 /* R */
+#define CPLD_ADDR_MODE_SET_0		0x0008 /* R */
+#define CPLD_ADDR_MODE_SET_1		0x0009 /* R */
+#define CPLD_ADDR_MODE_SET_2		0x000A /* R */
+#define CPLD_ADDR_MODE_SET_3		0x000B /* R */
+#define CPLD_ADDR_MODE_SET_4		0x000C /* R */
+#define CPLD_ADDR_MODE_LAST_0		0x0018 /* R */
+#define CPLD_ADDR_MODE_LAST_1		0x0019 /* R */
+#define CPLD_ADDR_MODE_LAST_2		0x001A /* R */
+#define CPLD_ADDR_MODE_LAST_3		0x001B /* R */
+#define CPLD_ADDR_MODE_LAST_4		0x001C /* R */
+#define CPLD_ADDR_DIPSW4		0x0020 /* R */
+#define CPLD_ADDR_DIPSW5		0x0021 /* R */
+#define CPLD_ADDR_RESET			0x0024 /* R/W */
+#define CPLD_ADDR_POWER_CFG		0x0025 /* R/W */
+#define CPLD_ADDR_PERI_CFG_0		0x0030 /* R/W */
+#define CPLD_ADDR_PERI_CFG_1		0x0031 /* R/W */
+#define CPLD_ADDR_PERI_CFG_2		0x0032 /* R/W */
+#define CPLD_ADDR_PERI_CFG_3		0x0033 /* R/W */
+#define CPLD_ADDR_LEDS			0x0034 /* R/W */
+#define CPLD_ADDR_LEDS_CFG		0x0035 /* R/W */
+#define CPLD_ADDR_UART_CFG		0x0036 /* R/W */
+#define CPLD_ADDR_UART_STATUS		0x0037 /* R */
+
+#define CPLD_ADDR_PCB_VERSION_0		0x1000 /* R */
+#define CPLD_ADDR_PCB_VERSION_1		0x1001 /* R */
+#define CPLD_ADDR_SOC_VERSION_0		0x1002 /* R */
+#define CPLD_ADDR_SOC_VERSION_1		0x1003 /* R */
+#define CPLD_ADDR_PCB_SN_0		0x1004 /* R */
+#define CPLD_ADDR_PCB_SN_1		0x1005 /* R */
+
+static u16 cpld_read(struct udevice *dev, u16 addr)
+{
+	u8 data[2];
+
+	/* Random flash reads require 2 reads: first read is unreliable */
+	if (addr >= CPLD_ADDR_PCB_VERSION_0)
+		dm_i2c_read(dev, addr, data, 2);
+
+	/* Only the second byte read is valid */
+	dm_i2c_read(dev, addr, data, 2);
+	return data[1];
+}
+
+static void cpld_write(struct udevice *dev, u16 addr, u8 data)
+{
+	dm_i2c_write(dev, addr, &data, 1);
+}
+
+static int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+	struct udevice *dev;
+	u16 addr, val;
+	int ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_SYSRESET,
+					  DM_DRIVER_GET(sysreset_renesas_v3hsk),
+					  &dev);
+	if (ret)
+		return ret;
+
+	if (argc == 2 && strcmp(argv[1], "info") == 0) {
+		printf("Product:                0x%08x\n",
+		       (cpld_read(dev, CPLD_ADDR_PRODUCT_3) << 24) |
+		       (cpld_read(dev, CPLD_ADDR_PRODUCT_2) << 16) |
+		       (cpld_read(dev, CPLD_ADDR_PRODUCT_1) << 8) |
+		       cpld_read(dev, CPLD_ADDR_PRODUCT_0));
+		printf("CPLD version:           0x%08x\n",
+		       (cpld_read(dev, CPLD_ADDR_CPLD_VERSION_Y_1) << 24) |
+		       (cpld_read(dev, CPLD_ADDR_CPLD_VERSION_Y_0) << 16) |
+		       (cpld_read(dev, CPLD_ADDR_CPLD_VERSION_M) << 8) |
+		       cpld_read(dev, CPLD_ADDR_CPLD_VERSION_D));
+		printf("Mode setting (MD0..26): 0x%08x\n",
+		       (cpld_read(dev, CPLD_ADDR_MODE_LAST_3) << 24) |
+		       (cpld_read(dev, CPLD_ADDR_MODE_LAST_2) << 16) |
+		       (cpld_read(dev, CPLD_ADDR_MODE_LAST_1) << 8) |
+		       cpld_read(dev, CPLD_ADDR_MODE_LAST_0));
+		printf("DIPSW (SW4, SW5):       0x%02x, 0x%x\n",
+		       cpld_read(dev, CPLD_ADDR_DIPSW4) ^ 0xff,
+		       (cpld_read(dev, CPLD_ADDR_DIPSW5) ^ 0xff) & 0xf);
+		printf("Power config:           0x%08x\n",
+		       cpld_read(dev, CPLD_ADDR_POWER_CFG));
+		printf("Periferals config:      0x%08x\n",
+		       (cpld_read(dev, CPLD_ADDR_PERI_CFG_3) << 24) |
+		       (cpld_read(dev, CPLD_ADDR_PERI_CFG_2) << 16) |
+		       (cpld_read(dev, CPLD_ADDR_PERI_CFG_1) << 8) |
+		       cpld_read(dev, CPLD_ADDR_PERI_CFG_0));
+		printf("PCB version:            %d.%d\n",
+		       cpld_read(dev, CPLD_ADDR_PCB_VERSION_1),
+		       cpld_read(dev, CPLD_ADDR_PCB_VERSION_0));
+		printf("SOC version:            %d.%d\n",
+		       cpld_read(dev, CPLD_ADDR_SOC_VERSION_1),
+		       cpld_read(dev, CPLD_ADDR_SOC_VERSION_0));
+		printf("PCB S/N:                %d\n",
+		       (cpld_read(dev, CPLD_ADDR_PCB_SN_1) << 8) |
+		       cpld_read(dev, CPLD_ADDR_PCB_SN_0));
+		return 0;
+	}
+
+	if (argc < 3)
+		return CMD_RET_USAGE;
+
+	addr = simple_strtoul(argv[2], NULL, 16);
+	if (!(addr >= CPLD_ADDR_PRODUCT_0 && addr <= CPLD_ADDR_UART_STATUS)) {
+		printf("cpld invalid addr\n");
+		return CMD_RET_USAGE;
+	}
+
+	if (argc == 3 && strcmp(argv[1], "read") == 0) {
+		printf("0x%x\n", cpld_read(dev, addr));
+	} else if (argc == 4 && strcmp(argv[1], "write") == 0) {
+		val = simple_strtoul(argv[3], NULL, 16);
+		cpld_write(dev, addr, val);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(cpld, 4, 1, do_cpld,
+	   "CPLD access",
+	   "info\n"
+	   "cpld read addr\n"
+	   "cpld write addr val\n"
+);
+
+static int renesas_v3hsk_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+	cpld_write(dev, CPLD_ADDR_RESET, 1);
+
+	return -EINPROGRESS;
+}
+
+static int renesas_v3hsk_sysreset_probe(struct udevice *dev)
+{
+	if (device_get_uclass_id(dev->parent) != UCLASS_I2C)
+		return -EPROTONOSUPPORT;
+
+	return 0;
+}
+
+static struct sysreset_ops renesas_v3hsk_sysreset = {
+	.request	= renesas_v3hsk_sysreset_request,
+};
+
+static const struct udevice_id renesas_v3hsk_sysreset_ids[] = {
+	{ .compatible = "renesas,v3hsk-cpld" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(sysreset_renesas_v3hsk) = {
+	.name		= "renesas_v3hsk_sysreset",
+	.id		= UCLASS_SYSRESET,
+	.ops		= &renesas_v3hsk_sysreset,
+	.probe		= renesas_v3hsk_sysreset_probe,
+	.of_match	= renesas_v3hsk_sysreset_ids,
+};
diff --git a/configs/r8a77980_v3hsk_defconfig b/configs/r8a77980_v3hsk_defconfig
new file mode 100644
index 0000000..564ff2d
--- /dev/null
+++ b/configs/r8a77980_v3hsk_defconfig
@@ -0,0 +1,83 @@
+CONFIG_ARM=y
+CONFIG_COUNTER_FREQUENCY=16666666
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_RMOBILE=y
+CONFIG_SYS_MALLOC_LEN=0x4000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_OFFSET=0x700000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="r8a77980-v3hsk-u-boot"
+CONFIG_SPL_TEXT_BASE=0xe6318000
+CONFIG_RCAR_GEN3=y
+CONFIG_R8A77980=y
+CONFIG_TARGET_V3HSK=y
+CONFIG_SPL_STACK=0xe6304000
+CONFIG_SYS_LOAD_ADDR=0x58000000
+CONFIG_LTO=y
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
+CONFIG_FIT=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_DEFAULT_FDT_FILE="r8a77980-v3hsk.dtb"
+# CONFIG_BOARD_EARLY_INIT_F is not set
+CONFIG_SYS_MALLOC_BOOTPARAMS=y
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0xe631f000
+CONFIG_SPL_BSS_MAX_SIZE=0x1000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_PBSIZE=2068
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_DTB_PROPS_REMOVE=y
+CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus"
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_RCAR_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_I2C=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_RENESAS_SDHI=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_BITBANGMII=y
+CONFIG_BITBANGMII_MULTI=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_SH_ETHER=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SCIF_CONSOLE=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_RENESAS_RPC_SPI=y
+CONFIG_SYSRESET=y
diff --git a/include/configs/v3hsk.h b/include/configs/v3hsk.h
new file mode 100644
index 0000000..58c2e88
--- /dev/null
+++ b/include/configs/v3hsk.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * include/configs/v3hsk.h
+ *     This file is V3HSK board configuration.
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation
+ * Copyright (C) 2019 Cogent Embedded, Inc.
+ */
+
+#ifndef __V3HSK_H
+#define __V3HSK_H
+
+#include "rcar-gen3-common.h"
+
+/* Environment compatibility */
+
+/* SH Ether */
+#define CFG_SH_ETHER_USE_PORT	0
+#define CFG_SH_ETHER_PHY_ADDR	0x0
+#define CFG_SH_ETHER_PHY_MODE	PHY_INTERFACE_MODE_RGMII_ID
+#define CFG_SH_ETHER_CACHE_WRITEBACK
+#define CFG_SH_ETHER_CACHE_INVALIDATE
+#define CFG_SH_ETHER_ALIGNE_SIZE	64
+
+/* Board Clock */
+/* XTAL_CLK : 33.33MHz */
+
+#endif /* __V3HSK_H */